Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks

Yang, Lei; Yan, Zheyu; Li, Meng; Kwon, Hyoukjun; Lai, Liangzhen; Krishna, Tushar; Chandra, Vikas; Jiang, Weiwen; Shi, Yiyu

doi:10.1109/dac18072.2020.9218676

Cited by 85 publications

(51 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Neural Architecture Search (NAS) has achieved state-of-the-art performance in various perceptual tasks, such as image classifications [22,23], inference security [2] and image segmentation [20].…”

Section: Neural Architecture Searchmentioning

confidence: 99%

Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search

Yan

Juan

et al. 2021

Proceedings of the 26th Asia and South Pacific Design Automation Conference

Self Cite

View full text Add to dashboard Cite

Emerging device-based Computing-in-memory (CiM) has been proved to be a promising candidate for high-energy efficiency deep neural network (DNN) computations. However, most emerging devices suffer uncertainty issues, resulting in a difference between actual data stored and the weight value it is designed to be. This leads to an accuracy drop from trained models to actually deployed platforms. In this work, we offer a thorough analysis of the effect of such uncertainties-induced changes in DNN models. To reduce the impact of device uncertainties, we propose UAE, an uncertaintyaware Neural Architecture Search scheme to identify a DNN model that is both accurate and robust against device uncertainties.

show abstract

Section: Neural Architecture Searchmentioning

confidence: 99%

Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search

Yan

Juan

et al. 2021

Proceedings of the 26th Asia and South Pacific Design Automation Conference

Self Cite

View full text Add to dashboard Cite

show abstract

“…Multiobjective NAS has been an active research topic during the last several years, and a large number of methods, capable of evaluating platform-dependent CNN metrics to assist it, have been proposed. [14] memory, latency, energy Roofline [30] latency low/ medium high X Specialized analytical methods [23] latency, energy, memory medium/ high low X [21], [31] latency, energy [19], [20], [22] latency, energy, throughput medium Measurements [32] latency high very low X [33] latency, energy Look-up tables (LUT) [34] latency high low X [35] latency high medium/ low ML [36] latency, energy high very low X [26] latency ALOHA this work latency, energy, throughput medium/ high high Every evaluation methods category is supplied with a list of methods belonging to it (Column 2), and characterized with: 1) the method accuracy (Column 4); 2) the method re-usability (Column 5); 3) modularity (Column 6). The method re-usability determines how sensitive the evaluation method category is to a specific CNN architecture or/and hardware platform, and determines the applicability of the evaluation method category.…”

Section: Related Workmentioning

confidence: 99%

“…as CPUs-GPUs platforms. Analogously, the work in [22] explores ASICs codesign, through performance evaluation based on MAESTRO [45], which makes the evaluation method, proposed in [22], only applicable to ASICs-based platforms. With the rapidly increasing number and diversity of devices, used to execute CNNs, such high specialization significantly limits the use of these methods.…”

Section: Related Workmentioning

confidence: 99%

ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge

Busia¹,

Minakova

Stefanov

et al. 2021

IEEE Access

View full text Add to dashboard Cite

CNN design and deployment on embedded edge-processing systems is an error-prone and effort-hungry process, that poses the need for accurate and effective automated assisting tools. In such tools, pre-evaluating the platform-aware CNN metrics such as latency, energy cost, and throughput is a key requirement for successfully reaching the implementation goals imposed by use-case constraints. Especially when more complex parallel and heterogeneous computing platforms are considered, currently utilized estimation methods are inaccurate or require a lot of characterization experiments and efforts. In this paper, we propose an alternative method, designed to be flexible, easy to use, and accurate at the same time. Considering a modular platform and execution model that adequately describes the details of the platform and the scheduling of different CNN operators on different platform processing elements, our method captures precisely operations and data transfers and their deployment on computing and communication resources, significantly improving the evaluation accuracy. We have tested our method on more than 2000 CNN layers, targeting an FPGA-based accelerator and a GPU platform as reference example architectures. Results have shown that our evaluation method increases the estimation precision by up to 5× for execution time, and by 2× for energy, compared to other widely used analytical methods. Moreover, we assessed the impact of the improved platform-awareness on a set of neural architecture search experiments, targeting both hardware platforms, and enforcing 2 sets of latency constraints, performing 5 trials on each search space, for a total number of 20 experiments. The predictability is improved by 4×, reaching, with respect to alternatives, selection results clearly more similar to those obtained with on-hardware measurements.

show abstract

“…In contrast to a state-of-the-art NAS, which often treats the target hardware as an abstract model, if at all, we have adapted our NAS specifically to our hardware architec-ture [22,23]. We can therefore incorporate prior knowledge about time series classification tasks.…”

Section: Neural Network Designmentioning

confidence: 99%

A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification

Reiser

Reichel

Pechmann

et al. 2021

JLPEA

View full text Add to dashboard Cite

In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.

show abstract

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks

Cited by 85 publications

References 13 publications

Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search

Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search

ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge

A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification

Contact Info

Product

Resources

About