cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System

LowLEAC: Low Leakage Energy Architecture for Caches

“…Hence, there is a need to reduce the penalty associated with capacity misses occurring due to the data lost by turning off cache lines. The dynamic power consumption by the cache is kept to a minimum by using CMOS compatible cNVSRAM memory cells [2]. Whenever a line is turned off, the data is saved in the non-volatile part of the cNVSRAM cell and can be retrieved from here, in case it is needed in the near future.…”

“…al. [2]. The cNVSRAM cache helps in reducing the performance penalty due to capacity misses and consumes less power as compared to conventional cache structures.…”

“…The cNVSRAM cache helps in reducing the performance penalty due to capacity misses and consumes less power as compared to conventional cache structures. In the normal operation mode, cNVSRAM uses a conventional 8T SRAM cell for its operation giving the same performance and dissipating leakage energy the same as an 8T The cache shown is an L1 data cache implemented using the cNVSRAM cells [2]. The control logic for cNVSRAM consists of the buffer with active cache line numbers.…”

“…For the cNVSRAM cells, we consider cell parameters based on 65 nm SMIC technology as described in [2]. has a minimum impact on the restoration time which is limited to 11 ps.…”

“…has a minimum impact on the restoration time which is limited to 11 ps. The ratio of C2/C1 is 14 and their sizes are W c1 = 120 nm, L c1 = 60 nm, W c2 = 420 nm, and L c2 = 240 nm [2].…”