CMOS technology scaling and its implications

Iizuka, Tetsuya

doi:10.1017/cbo9781316156148.002

Cited by 5 publications

(1 citation statement)

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“…A significant challenge related to the design of many-cores in recent technology nodes is the increased power density, which causes the effect called Dark Silicon [2], where parts of the circuit need to be switched-off (dark) or underclocked to keep the system within the physical limits of power density and safe temperature. Although the number of PEs increases in many-core designs, the power consumed by each PE remains constant, since the threshold and supply voltage does not scale down with the size of the transistor as in previous technologies [3,4].…”

Section: Introductionmentioning

confidence: 99%

Mapping and Migration Strategies for Thermal Management in Many-Core Systems

Silva

Martins

Moraes

2020

2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)

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New technology nodes enable the integration of billions of transistors in a small silicon area by replicating identical structures, resulting in many-core systems. However, power density may limit the amount of energy the system can consume. A many-core at its maximum performance may lead to safe temperature violations and, consequently, result in reliability issues. Dynamic Thermal Management (DTM) techniques proposals guarantee that many-core systems run at good performance without compromising reliability. In this paper, we review recent DTM works, discussing their limitations, and propose new heuristics for thermal-aware application mapping and migration, using a hardware accelerator that enables temperature monitoring on systems with a large number of processing elements. Results show that using straightforward heuristics, with reactive actions based on runtime temperature monitoring, reduce the peak temperature in high workload scenarios (6.8%), and improve thermal distribution significantly on a large (8x8) many-core system.

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Section: Introductionmentioning

confidence: 99%