CMOS technology for MS/RF SoC

Adaptive Resolution ADC Array for an Implantable Neural Sensor

“…A rough estimate of the SAR power consumption can be found by assuming that all of the flip-flops are asynchronous settable and resettable and contain 2 NOR gates, 2 nand and 2 inverters [11], approximately equivalent to 5 nand gates. Further, assuming that all of these gates switch at frequency , where is the signal bandwidth, then we have a close upper bound on the SAR dynamic power consumption as given (3) The comparator power consumption can be estimated as (4) using the comparator power bound formula from (15) and recognizing that 1) the SAR has only one comparator and 2) the comparator switching rate increases by a factor with respect to the comparator in a flash ADC. These power bounds are combined to give an estimate on the power consumption of a CR-SAR ADC (5) Equations (2)- (4), together, with process constants for a typical 0.13-m process are substituted into (5) to generate curve CR SAR in Fig.…”

“…Reference [15] reports that % m is typical for 0.13-m CMOS but this varies across processes. We restrict our design to using particular foundry recommended capacitor structures, overdesign for capacitor mismatch by a factor of two from this theoretical value, to accommodate variation and additional errors due to routing mismatch.…”

“…The derivation of power bounds and particularly (15) suggest that an appropriate figure of merit (FOM) for matching limited converters is given by (11). This FOM corresponds to energy dissipation per conversion step and is a widely employed metric conversion step (11) where is the sampling rate in the case of a Nyquist rate converter.…”

“…In 0.13-m CMOS, is about 4.5 mV m. From the observation that the energy required to switch a latch pair of transistors from the metastable state to a fixed state with one-certainty is (13) where is the gate-oxide capacitance per-unit area, Pelgrom [27] derives the minimum ADC energy per step size per pair of matching critical transistors, to ensure that a least-siginificant bit (LSB) change in the input is detected when matching limited Power (14) where is the number of bits to be decoded, is the signal bandwidth, and is chosen to be equal to 10 to allow giving a confidence interval assuming a Gaussian distribution in mismatch. Simple algebraic manipulation gives a power bound for matching-limited flash ADCs with more familiar process constants (15) where is the total number of pairs of matching critical transistors per comparator and is the total number of comparators.…”

“…So the lower bound on power consumption for a flash should be between (15) and (16) for this application. Equation (16) is plotted as a curve Murmann Flash in Fig.…”