CMOS Small-Signal and Thermal Noise Modeling at High Frequencies

Antonopoulos, Angelos; Bucher, Matthias; Papathanasiou, K.; Mavredakis, Nikolaos; Makris, Nikolaos; Sharma, Rupendra Kumar; Sakalas, P.; Schröter, M.

doi:10.1109/ted.2013.2283511

Cited by 29 publications

(15 citation statements)

References 41 publications

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“…Short channel e®ects such as velocity saturation and channel length modulation are responsible for the signi¯cant increase in the thermal noise excess factor in deep submicron CMOS technologies. 28,29 Thus, thermal noise from the active devices is usually the principal source of white noise in the output spectrum as already observed from Figs. 6-8.…”

Section: ½Zfá!gj Whitementioning

confidence: 59%

Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair

Chlis

Pepe²,

Zito

2015

J CIRCUIT SYST COMP

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Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong di®erential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of¯ve distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of°icker noise contribution as the major e®ect leading to phase noise degradation in nanoscale CMOS LC oscillators.

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Section: ½Zfá!gj Whitementioning

confidence: 59%

Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair

Chlis

Pepe²,

Zito

2015

J CIRCUIT SYST COMP

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“…In order to account for the increase of γ n in SI [12], we have modeled it as a function of IC according to Figure 8 which is consistent with the γ n presented in [12]. We can observe in Figure 9 that for a long-channel device, the deeper we are in SI, the better the phase noise is.…”

mentioning

confidence: 58%

“…The transistors M 1 and M 2 should be matched, and their gate width is determined exactly as in (12). The variation of W g as a function of IC has the same trend as the one shown in Figure 5.…”

Section: Linear Analysismentioning

confidence: 89%

Design of ultra low‐power RF oscillators based on the inversion coefficient methodology using BSIM6 model

Guitton

Mangla

Chalkiadaki

et al. 2015

Circuit Theory & Apps

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SUMMARYThis paper presents a fast and accurate way to design and optimize LC oscillators using the inversion coefficient (IC). This methodology consists of four steps: linear analysis, nonlinear analysis, phase noise analysis, and optimization using a figure of merit. For given amplitude of oscillation and frequency, we are able to determine all the design variables in order to get the best trade-off between current consumption and phase noise. This methodology is demonstrated through the design of Pierce and cross-coupled oscillators and has been verified with BSIM6 metal oxide semiconductor field effect transistor compact model using the parameters of a commercial advanced 40 nm complementary metal oxide semiconductor process.

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“…The EKV2.6 model includes thermal noise as well as low frequency noise. Thermal noise uses a charge-based expression without parameters, while low frequency noise model is of the 1/f noise type and uses three parameters [9]. Measured noise spectra at low frequencies are shown in Fig.…”

Section: Noise Characterization and Modelingmentioning

confidence: 99%

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Grabinski¹,

Abo-Elhadid

Mierzwinski

et al. 2019

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)

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The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

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CMOS Small-Signal and Thermal Noise Modeling at High Frequencies

Cited by 29 publications

References 41 publications

Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair

Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair

Design of ultra low‐power RF oscillators based on the inversion coefficient methodology using BSIM6 model

FOSS EKV2.6 Verilog-A Compact MOSFET Model

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