[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOI: 10.1109/iccd.1991.139900
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CMOS processor circuit design in Hewlett-Packard's series 700 workstations

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“…The data interface is 64-bits wide for each cache. The cache pipelines have been described previously [4]. The instruction cache interface delivers a pair of instructions each clock cycle.…”
Section: Cache and Memory Subsystemsmentioning
confidence: 99%
“…The data interface is 64-bits wide for each cache. The cache pipelines have been described previously [4]. The instruction cache interface delivers a pair of instructions each clock cycle.…”
Section: Cache and Memory Subsystemsmentioning
confidence: 99%