2020
DOI: 10.1109/access.2019.2960684
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CMOS Position-Based Charge Qubits: Theoretical Analysis of Control and Entanglement

Abstract: In this study, a formal definition, robustness analysis and discussion on the control of a position-based semiconductor charge qubit are presented. Such a qubit can be realized in a chain of coupled quantum dots, forming a register of charge-coupled transistor-like devices, and is intended for CMOS implementation in scalable quantum computers. We discuss the construction and operation of this qubit, its Bloch sphere, and relation with maximally localized Wannier functions which define its positionbased nature.… Show more

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Cited by 27 publications
(35 citation statements)
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References 58 publications
(94 reference statements)
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“…Fig. 1 presents an overview of the CMOS position-based charge qubit structure containing an array of QDs [9], [11], [12], with schematics of nearby interfacing circuitry: reset, control, singleelectron injector, and detector. It is part of a quantum processor implemented in 22-nm FDSOI CMOS and operating at cryogenic temperature of 3.4 K, whose earlier version was presented in [10].…”
Section: A Imposer/injector Topologymentioning
confidence: 99%
See 4 more Smart Citations
“…Fig. 1 presents an overview of the CMOS position-based charge qubit structure containing an array of QDs [9], [11], [12], with schematics of nearby interfacing circuitry: reset, control, singleelectron injector, and detector. It is part of a quantum processor implemented in 22-nm FDSOI CMOS and operating at cryogenic temperature of 3.4 K, whose earlier version was presented in [10].…”
Section: A Imposer/injector Topologymentioning
confidence: 99%
“…Table I summarizes the key specifications for the CDAC in the proposed system. The values are derived from physical equations and COMSOL multiphysics modeling of the QDA structures [9], [11]. To overcome the kT/q thermal energy of an electron, the LSB voltage step (i.e., resolution) at the tunnel junction between QDs should be finer than 300 µV at 4 K. However, the voltage applied at the imposer gates should be ∼10× larger due to the capacitive division between C ox (gate oxide capacitance) and C t (tunnel junction capacitance).…”
Section: A Imposer/injector Topologymentioning
confidence: 99%
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