CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

Hossain, Masum; Carusone, Anthony Chan

doi:10.1109/jssc.2009.2022917

Cited by 56 publications

(31 citation statements)

References 21 publications

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“…However, the injection locking is weak at this extreme phase shift. In order to make the system more robust and provide additional phase shift, additional weighted phase inversions of the injected signal can be employed [21].…”

Section: Ilo De-skewmentioning

confidence: 99%

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Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

Liu

Chiang

et al. 2011

Journal of Electrical and Computer Engineering

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High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be leveraged to provide additional jitter filtering at the receiver. Jitter tolerance analysis for a 10 Gb/s system shows that a near all-pass delay-locked loop (DLL) and phase-interpolator-(PI-) based de-skew performs best under low skew conditions, while, at high skew, architectures which leverage band-pass clock filtering or a phase-locked loop (PLL) for increased jitter filtering are more suitable. De-skew based on injection-locked oscillators (ILOs) offer a reduced complexity design and competitive jitter tolerance over a wide skew range.

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Section: Ilo De-skewmentioning

confidence: 99%

“…If S inj is the injected clock phase noise and S osc is the de-skew oscillator phase noise, then the output phase noise, S out , at a given frequency, ω, can be expressed in terms of frequency offset Δω or de-skewed output phase shift θ ss [21]:…”

Section: Ilo De-skewmentioning

confidence: 99%

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

Liu

Chiang

et al. 2011

Journal of Electrical and Computer Engineering

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“…To ensure uniqueness of the phase codes, this work adopts the concept of I/Q injection from [3], but adds calibration that finds the switchover points between the I and Q phase tuning curves. The ILO output is compared, using zero and quadrature phase detectors, to a reference corresponding to 0° (point E in In this work, the 0° reference is generated from a replica ILO, simultaneously injected at both I and Q while keeping Δω=0, as shown in Fig.…”

Section: Ilo Phase Rotators For Mobile Memory I/omentioning

confidence: 99%

“…To cover the range of ±90° (the full 360° can be achieved by adding an inversion in the path), |Δω|=|ω 0 -ω inj | needs to become large, causing waveform degradation, potential loss of lock, nonlinearity of the phase response, and variation of the jittertracking bandwidth [2]. In [3], this was mitigated by introducing multi-node injection: by injecting at I or Q nodes of the quadrature ILO, two different phase tuning curves are generated, covering -90° to 0° and 0° to +90°, respectively [ Fig. 1].…”

Section: Introductionmentioning

confidence: 99%

“…While the schemes in [2] and [3] are attractive from the power savings standpoint as they only require a single-phase global clock distribution, their drawback is that the system does not know when the ILO is reaching the edge of its locking range, or when to switch from one phase tuning curve to another. This is especially true in presence of process, voltage and temperature variations.…”

Section: Introductionmentioning

confidence: 99%

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A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS

Aleksic

2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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This paper presents a 7-bit 3.2-GHz injectionlocked oscillator (ILO) based phase rotator for burst-mode mobile memory I/O. Phase shifting is achieved by selecting the injection point and offsetting the natural frequency of the ILO from that of the injected clock. The circuit implements two techniques that enable its use in burst-mode systems: 1) synchronous stopping and restarting of the ILO achieved by strong injection, as opposed to a relatively weak injection during normal operation, and 2) phase characteristic calibration that allows continuous, infinite-throw phase rotation needed for link timing calibration. The circuit is implemented in a 1-V low-leakage 28-nm CMOS process. Power consumption and area are 1.3 mW and 0.03 mm 2 .

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