CMOS LNA design for system-on-chip receiver stages

Telli, Ali; Askar, M.

doi:10.1109/smic.2004.1398195

Cited by 4 publications

(2 citation statements)

References 9 publications

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“…For many narrow-band RF applications, the cascode inductively degenerated CMOS LNA topology, depicted in Fig. 1, achieves better performance than its counterparts that use resistors or active components for biasing and impedance matching [10][11][12]. The design of the LNA is complex since both input and output impedance matching must minimize the reflection coefficients to maximize the power transfer while the gain, noise figure, and power dissipation must meet the requirements of the complete RF system.…”

Section: General Lna Design Considerationsmentioning

confidence: 99%

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Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

Ragheb

Nieuwoudt

Massoud

2007

Analog Integr Circ Sig Process

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In this paper, we present an analytical modeling methodology for fully integrated inductively-degenerated CMOS narrow-band cascode Low Noise Amplifiers (LNA) that captures short channel transistor effects to enable rapid design space exploration in current and future process technologies. The modeling methodology captures the impact of parasitics on passive components, ESD-protection structures, and devices to accurately predict both impedance matching and noise figure. Our modeling is suitable for numerical optimization and fully automated synthesis for LNAs. The results indicate that the methodology models ESD-protected LNA circuits with 47.9% better accuracy in noise figure when compared with several current analytical modeling techniques with four orders of magnitude improvement in simulation time over circuitlevel simulation. Given its speed and accuracy, the analytical modeling methodology is well-suited for design space exploration.

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Section: General Lna Design Considerationsmentioning

confidence: 99%

“…The third terms in (11) and (12) are the result of correlation between the gate and drain noise in M 1 and M 2 , respectively [4].…”

Section: Noise Figurementioning

confidence: 99%

Parasitic-aware analytical modeling of integrated CMOS inductively degenerated narrow-band low noise amplifiers

Ragheb

Nieuwoudt

Massoud

2007

Analog Integr Circ Sig Process

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A low voltage current mode CMOS integrated receiver front-end for GPS system

Cheng

Chan

Pun

et al. 2009

Analog Integr Circ Sig Process

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This paper presents a low voltage, 1.6 GHz integrated receiver front-end which is implemented by the standard 0.35 lm, 3M2P CMOS technology. The receiver consists of a transconductance low noise amplifier (G m -LNA), a down conversion current mode mixer and a voltage-controlled oscillator using accumulation-mode MOS varactor (A-MOS VCO). A current mode mixer is used to reduce the supply voltage to 1 V. A specially designed G m -LNA converts RF input voltage to RF input current for the current mode mixer. This could eliminate an unnecessary I-V, V-I conversion and reduce the non-linearity contribution. Moreover, a low voltage A-MOS VCO, with a good phase noise and wide tuning frequency range, is used to generate a required oscillating frequency for the receiver. The integrated receiver front-end has a measured power conversion gain of 11.4 dB, an input referred thirdorder intercept point (IIP 3 ) of 6.1 dBm, and a noise figure of 5.87 dB. The measured total power consumption is 40.9 mW with 1 V supply.

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