CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

Chen, Wei-Hao; Dou, Chunmeng; Li, Kaixiang; Lin, Wei‐Yu; Li, Pinyi; Huang, Jianhao; Wang, Jinghong; Wei, Weichen; Xue, Cheng-Xin; Chiu, Yen-Cheng; King, Ya‐Chin; Lin, Chorng-Jung; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Yang, J. Joshua; Ho, Mon−Shu; Chang, Meng‐Fan

doi:10.1038/s41928-019-0288-0

Cited by 182 publications

(70 citation statements)

References 40 publications

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“…Aspects of a fully-integrated chip that are not entirely captured in our experiments such as IR drop and additional circuit nonidealities such as offsets and noise have been studied in previous works and could be mitigated by additional retraining methods 18,20 . Experiments on fully-integrated memristor chips could be used to faithfully quantify their impact on the inference accuracy 7,9,46 . With respect to device yield, additional simulations showed that additive noise training also helps to mitigate the impact of devices stuck at low or high conductance on the inference accuracy (see Supplementary Fig.…”

Section: Discussionmentioning

confidence: 99%

“…In order to reduce the data transfers to a minimum in inference accelerators, a promising avenue is to employ in-memory computing using non-volatile memory devices [3][4][5] . Both charge-based storage devices, such as Flash memory 6 , and resistance-based (memristive) storage devices, such as metal-oxide resistive randomaccess memory [7][8][9][10] and phase-change memory (PCM) [11][12][13][14] are being investigated for this. In this approach, the network weights are encoded as the analog charge state or conductance state of these devices organized in crossbar arrays, and the matrix-vector multiplications during inference can be performed in-situ in a single time step by exploiting Kirchhoff's circuit laws.…”

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confidence: 99%

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Accurate deep neural network inference using computational phase-change memory

Joshi¹,

Gallo²,

Haefeli³

et al. 2020

Nat Commun

339

323

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In-memory computing using resistive memory devices is a promising non-von Neumann approach for making energy-efficient deep learning inference hardware. However, due to device variability and noise, the network needs to be trained in a specific way so that transferring the digitally trained weights to the analog resistive memory devices will not result in significant loss of accuracy. Here, we introduce a methodology to train ResNet-type convolutional neural networks that results in no appreciable accuracy loss when transferring weights to phase-change memory (PCM) devices. We also propose a compensation technique that exploits the batch normalization parameters to improve the accuracy retention over time. We achieve a classification accuracy of 93.7% on CIFAR-10 and a top-1 accuracy of 71.6% on ImageNet benchmarks after mapping the trained weights to PCM. Our hardware results on CIFAR-10 with ResNet-32 demonstrate an accuracy above 93.5% retained over a one-day period, where each of the 361,722 synaptic weights is programmed on just two PCM devices organized in a differential configuration.

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Section: Discussionmentioning

confidence: 99%

mentioning

confidence: 99%

Accurate deep neural network inference using computational phase-change memory

Joshi¹,

Gallo²,

Haefeli³

et al. 2020

Nat Commun

339

323

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show abstract

“…An ANN model requires complex peripheral circuits. Previous research into ANNs implemented in integrated circuits focused on devices built from memristors or flash memories 12,62 that can perform analog MAC operations 11,14,22,29 . However, most results lacked activation function and weight update circuits or were complemented by peripheral silicon circuits, without which a neural network is merely a linear regression model.…”

Section: Circuit Architecturementioning

confidence: 99%

“…Under the same signal energy, the signal-to-noise ratio is sufficiently large that analog convolution calculations can be performed. Moreover, by choosing different voltage ranges, a desirable relationship between the measured current and applied voltage can be obtained when implementing analog matrix computation 12 . Therefore, TMDs are ideal transistor candidates for implementing ANNs in application-specific integrated circuits 60 , as they offer an advantageous combination of established sensing capabilities and outstanding transistor performance.…”

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confidence: 99%

An Artificial Neutral Network Chip Based on Two-Dimensional Semiconductor

Chen

et al. 2020

Preprint

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Two-dimensional semiconductors can be used to build integrated circuits for running artificial neural networks (ANN) with higher energy efficiency. The implementation of an ANN with 2D semiconductors has been held back by the large-scale and high-quality transistors required for running machine learning algorithms. Here we demonstrate the first functional MoS2 analog ANN integrated circuit, including memory, multiply-and-accumulate (MAC), activation function, and weight update circuits. The ANN integrated circuit is realized through 818 field effect transistors (FETs) with wafer-scale and high-homogeneity MoS2 film. The large current on/off ratio and output linearity of these MoS2 FETs allow the realization of convolutional and activation function circuits with a few number of transistors. This ANN can be used for recognizing tactile digit, showing the recognition rate exceeding 97%. Our work demonstrates wafer-scale processing of a 2D semiconductor for building integrated circuits with the functions of AI computation.

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“…MLC-based computing is promising when targeting applications with intensive multiply-accumulate operations, such as convolutional neural networks (CNN) [19]. However, a number of challenges remain in terms of manufacturability and computational accuracy regarding device variability, pattern-dependent current leakage and the area overhead of peripheral circuits [20]. Major semiconductor foundries have not included MLC technology in their development roadmaps in the near future [19].…”

Section: Introductionmentioning

confidence: 99%

Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

Ali

Rizk

Baghdadi

et al. 2020

IEEE Trans. VLSI Syst.

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In this paper, we present a novel logic design style, namely memristor overwrite logic (MOL), associated with an original MOL-based computational memory. MOL relies on a fully digital representation of memristor and can operate with different memristive device technologies. Its integration in memristive crossbar arrays and computational memories allows the execution of bit and vector-level primitive logic operations in two computational steps at most. Promising features and performances are demonstrated through the implementation of N-bit full addition using the proposed MOL-based computational memory.

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CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

Cited by 182 publications

References 40 publications

Accurate deep neural network inference using computational phase-change memory

Accurate deep neural network inference using computational phase-change memory

An Artificial Neutral Network Chip Based on Two-Dimensional Semiconductor

Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

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