CMOS floating gate defect detection using I/sub DDQ/ test with DC power supply superposed by AC component

Abstract

Abstract

Improvement of detectability for CMOS floating gate defects in supply current test

“…In our test method, an AC component is superposed on DC power supply [6]. Figure 1 shows the test circuit attached to a NAND gate.…”

“…It intends to excite the defective node with the electric field so that some abnormal supply current flows. We also proposed a supply current test method in which the floating node is excited by a sinusoidal signal superposed on the supply voltage [6]. By the use of either method, we can detect existence of some defects with the supply current increase caused by conduction of a defective transistor in a DUT.…”

“…In the next section, we describe the test method [6] for the study. In the succeeding section, we propose a new way for detecting the floating gate defects in CMOS ICs.…”

Analogue diagnosis of CMOS floating gate defect (FGD) using Genetic Algorithms (GAs)

“…poly to bulk capacitance C pb are unpredictable a prior of defect occurred. Single testing strategy from logical and functional test is incompatible to detect all the defective current corresponded to typical range of C pb [2]. The defective outputs might be saturated at detectable, undefined or undetectable output levels depend on the values of C pb and its defect location as well.…”