CMOS Demonstration of Negative Capacitance HfO<sub>2</sub>-ZrO<sub>2</sub> Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process

Shanker, Nirmaan; Cook, Matthew; Cheema, Suraj; Li, W.; Rastogi, Ravi; Pipitone, Dominick; Chen, C.; Smith, Matthew W.; Meninger, Scott; Bauer, Florian; Pinelli, Gianni; Hunt, Josh; Salahuddin, Sayeef; Mohamed, M.

doi:10.1109/iedm45625.2022.10019472

2022 International Electron Devices Meeting (IEDM) 2022

DOI: 10.1109/iedm45625.2022.10019472

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CMOS Demonstration of Negative Capacitance HfO₂-ZrO₂ Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process

Nirmaan Shanker

Matthew Cook

Suraj Cheema

et al.

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CMOS Demonstration of Negative Capacitance HfO₂-ZrO₂ Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process

Cited by 4 publications

References 8 publications

Boost in Carrier Velocity Due to Electrostatic Effects of Negative Capacitance Gate Stack

Boost in Carrier Velocity Due to Electrostatic Effects of Negative Capacitance Gate Stack

Demonstration of EOT-Scaled FinFET Based on Thickness-Proportion Controlled HZH Superlattice Gate Stacks With Improved Thermal Stability (≥ 450 °C)

Enhanced Memory Window and Excellent Endurance in FeFET With Ultrathin 2DEG Oxide Channel

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CMOS Demonstration of Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process

Cited by 4 publications

References 8 publications

Boost in Carrier Velocity Due to Electrostatic Effects of Negative Capacitance Gate Stack

Boost in Carrier Velocity Due to Electrostatic Effects of Negative Capacitance Gate Stack

Demonstration of EOT-Scaled FinFET Based on Thickness-Proportion Controlled HZH Superlattice Gate Stacks With Improved Thermal Stability (≥ 450 °C)

Enhanced Memory Window and Excellent Endurance in FeFET With Ultrathin 2DEG Oxide Channel

Contact Info

Product

Resources

About

CMOS Demonstration of Negative Capacitance HfO₂-ZrO₂ Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process