CMOS blocks for on-chip RF test

Abstract

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test-and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35 µm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.

Built-in Loopback Test for IC RF Transceivers

“…Circuit implementations of TAs with the input 20 dBm have been reported [26], [30], [37]. The TA circuit can be disabled in the normal operation mode in order not to affect the chip performance.…”

“…2] (18) we find the corresponding sensitivities to the mixer parameters to be attenuated by the LNA gain. To overcome this drawback the bypassing technique can be used [30], [38]. Fault diagnosis is also supported in this way.…”

“…A loopback element, usually an attenuator, between the transmitter output and receiver input is required to match the signal level. In normal operation mode the loopback attenuator can be disabled so that the transceiver performance is practically not affected [30]. On the other hand, this technique makes parametric fault detection and fault diagnosis difficult for limited controllability and observability.…”

Multiband RF-sampling receiver front-end with on-chip testability in 0.13 μm CMOS

“…Another implementation using poly resistors suffers from several drawbacks like larger chip area, high parasitic capacitances, and changes in sheet resistance due to process variation and mismatch. Compared to T or bridged-T network the p-network is better suited to provide 50 X impedance matching and higher attenuation values [20].…”

An On-Chip Loopback Block for RF Transceiver Built-In Test

“…Hence, on-chip loopback has the potential to increase coverage at the wafer test stage and to reduce test costs, as well as to develop in-field selfchecks and calibration without external resources during the transceiver lifetime for enhanced reliability. Moving toward this goal, on-chip block-level characterizations of critical loopback components (e.g., switches and attenuators) were performed in [11] and [12]. In comparison, with loopback on the load board, any on-chip components are prone to parameter variations and more likely to fail, which creates design and characterization challenges to be addressed in research and practice.…”