Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors

Abstract

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Hierarchical Instruction Register Organization

“…Approaches have included instruction compression and scheduling to minimize the instruction bus activity factor [5]. The indexed IRF architecture effectively implements compressed instruction loads, but could potentially benefit from wire activity-aware scheduling.…”

“…These two approaches have been shown to reduce instruction fetch power by 58% and 60% relative to a standard I-cache, respectively [6], [2]. Clustered loop buffers [5] were proposed to build an efficient and scalable loop buffer for an 8-wide VLIW processor, achieving 63% energy savings. Their implementation is similar to the Distributed Indexed configuration described here, but their distributed control resulted in worse efficiency, possibly due to disregarding the wire energy.…”

Joint hardware–software leakage minimization approach for the register file of VLIW embedded architectures

“…The loop buffer is used when the processor is running a loopdominated code and the instructions are fetched from the L1 Instruction Memory. For further details on the loop buffer and its operation, the reader is referred to [42]. Both types of caches (data and instruction) are connected to a unified level 2 cache, which is in turn connected to an external memory.…”

“…1 shows two data clusters, where each cluster contains three functional units. Next, an instruction cluster is formed by using a distributed instruction buffer (also called loop buffer [42,43]) across multiple-issue slots of the VLIW processor. Fig.…”

Fine-grain dynamic instruction placement for L0 scratch-pad memory

“…For example, instruction cache contributes to 27% of the total energy consumed in the StrongARM processor [30]. To reduce instruction delivery energy (which in this paper refers to the energy consumed in instruction storage hierarchy), researchers have proposed extending the hierarchy by adding small instruction stores (typically 1KB or smaller) between the L1 instruction cache and the processor [25,28,29,14,24, * This work was done when the author was at Stanford University.…”