Closed-form crosstalk noise metrics for physical design applications

Chen, L.H.; Marek-Sadowska, M.

doi:10.1109/date.2002.998392

Cited by 14 publications

(9 citation statements)

References 14 publications

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“…The moments obtained using SMC in Section II can be used for model order reduction or direct moment metrics. For RC circuits, the work in [10] used two orders of moment for delay estimation while the authors of [12] and [13] used up to first three orders of moments for crosstalk noise analysis. For RLC circuits, moment based timing metrics are used in [9], [11].…”

Section: Directly Mapped Pdfs For Statistical Signal Integrity Anmentioning

confidence: 99%

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Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees

Hao

Shi

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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Section: Directly Mapped Pdfs For Statistical Signal Integrity Anmentioning

confidence: 99%

“…For coupled RC circuits, simple metrics based on moments for crosstalk analysis are reported in [12], [13], [14]. However, for RLC circuits with strong inductance effects, there do not exist simple yet accurate metrics.…”

Section: Introductionmentioning

confidence: 98%

Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees

Hao

Shi

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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“…As a result, complex noise superposition models, which have been shown to offer more reliable delay estimates in the presence of crosstalk, have been developed [4], [6]. In [7], closed form expressions for the total noise waveform due to all active neighbors of a wire was proposed for local wires but is seamlessly extendable to long wire interconnect structures.…”

Section: Related Workmentioning

confidence: 99%

“…Our proposed approach makes two key contributions: First, using the noise model proposed in [7] for the crosstalk noise waveform, we propose an efficient corresponding delay model as a function of inter-signal input skew for a typical segment in a multi-segment interconnect (MSI). Second, unlike in [9], we propose staggered latching, a novel synchronous clocking strategy that efficiently leverages skewed switching with no additional bus wire overhead.…”

Section: Related Workmentioning

confidence: 99%

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

Eze

Öztürk

Narayanan

2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed.

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“…These methods use either transient analysis techniques [1] or closed-form equations which capture the transient effects [2]. Techniques for crosstalk estimation at the layout-level have been proposed in [3] [4][5] [6].…”

Section: Introduction and Related Workmentioning

confidence: 99%

Floorplan-based crosstalk estimation for macrocell-based designs

Gupta

Katkoori

Sankaran

18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design

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We propose an estimation technique to measure the crosstalk susceptibility of different nets in the post global routing phase, prior to detailed routing of designs. Global routing provides the approximate routes of the wires. This is used to compute the aggressors of a given victim wire along its route and its crosstalk susceptibility with respect to those aggressors. The crosstalk susceptibility of a victim wire is given by (1) P t , the probability of crosstalk occurrence on the wire in different regions along its route; and (2) V peak , the worst case noise amplitude experienced by the wire along its route. P t is estimated using a very fast and accurate statistical estimator previously proposed by the authors. V peak is estimated by predicting the cross-coupling capacitances between neighboring wires, using their global routing information. Placement and global routing are done using CADENCE Silicon Ensemble. The predicted crosstalk estimates are compared against those by detailed HSPICE simulations. Average errors are found to be less than 8% while the execution times are significantly reduced.

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Closed-form crosstalk noise metrics for physical design applications

Cited by 14 publications

References 14 publications

Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees

Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

Floorplan-based crosstalk estimation for macrocell-based designs

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