Clocking of Synchronous Circuits

Abstract

Up to this point, we have ignored the difficulties of distributing a clock signal over a chip or a major portion thereof. We were in good company as systems engineering, automata theory, and other theoretical underpinnings of digital design assume simultaneous updating of state throughout a circuit. Physical reality is different from such abstractions, though. scan in Sci_TI clock domain or entire IC Clk_CI clock inputFIGURE 7.1Clock distribution. Clock domain with clock distribution network, scan path, and just one combinational propagation path shown (a), relevant timing quantities (b). Top-Down Digital VLSI DesignDesigning dependable circuits in spite of clock skew and jitter involves two issues, namely (a) knowing and lowering the vulnerability of a design, and (b) minimizing scattering by distributing clock signals over a domain in an adequate way.The two issues will be discussed in sections 7.2 and 7.3 respectively. For simplicity, we will focus on signals that circulate within one clock domain, thereby dropping any input and output signals from our analysis in section 7.2. Synchronous I/O is addressed in section 7.4, whereas the problems associated with assimilating data that arrive asynchronously are postponed to chapter 8. How to safely implement clock gating is the subject of section 7.5.1 Experienced designers sometimes introduce clock skew on purpose either to accommodate RAMs and other subcircuits with larger-than-normal setup/hold times or to allow for faster clocking by adapting to uneven path delays. A better tolerance with respect to delay variations may also be sought in this way, see problem 2. The process of tuning a clock distribution network to local timing requirements is termed clock skew scheduling, aka useful skew. Please refer to problem 8 and to the specialized literature [174] [175] [176] for more details on this optimization technique.