Clock sensitivity reduction in echo cancellers

Cox, S. A.

doi:10.1049/el:19850412

Cited by 13 publications

(4 citation statements)

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“…The term has a power series expansion which, if truncated to the first two terms, gives (10) Then, taking an inverse Fourier transform we get (11) a formula for the linear interpolation in the time-domain. The above result indicates clearly the limitations of the linear interpolator [12].…”

Section: Phase Correction In Frequency-domain (Dft)mentioning

confidence: 61%

“…The signal that is delivered to the EC is given by (12) where depicts an echo impulse response in the timedomain, is a symbol value, e.g., 1, 3 for the 2B1Q code, is a sampling instant, is a sampling interval . The assumed signal length-which is theoretically, infinite-is limited to 80 consecutive previous symbols during the simulation.…”

Section: Phase Correction In Frequency-domain (Dft)mentioning

confidence: 99%

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Frequency-domain echo canceller with phase adjustment

Fertner

1997

IEEE Trans. Circuits Syst. II

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The frequency-domain filter is an efficient realization of an echo canceller that provides a simple and elegant solution to the problem of jitter compensation. An essential requirement for a low-error digital transmission system is that the echo canceller retains high accuracy while the sampling instant is being adjusted. The one of the most attractive features of discrete Fourier transform is its capacity to reconstruct time-shifted signals using phase shifts in the frequency-domain. The signals involved, however, are not always alias-free (nor are they in telecommunications), which seriously degrade the echo cancellation. This paper introduces a de-aliasing technique, which results in an algorithm that is largely insensitive to the spectral content of cancelled signals. The de-aliasing technique allows to preserve high-performance echo cancellation during rapid changes in the sampling phase of the input signal. Computer simulations confirm the theoretically predicted behavior and accuracy.

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Section: Phase Correction In Frequency-domain (Dft)mentioning

confidence: 61%

Section: Phase Correction In Frequency-domain (Dft)mentioning

confidence: 99%

Frequency-domain echo canceller with phase adjustment

Fertner

1997

IEEE Trans. Circuits Syst. II

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“…The compensators are described in detail elsewhere [14][15][16][17][18]. Figure 5 shows the signal processing required for a linear echo canceller tap with both nonlinearity and jitter compensation.…”

Section: Echo Cancellationmentioning

confidence: 99%

A long reach digital subscriber loop transceiver

Adams¹,

Cox²,

Carpenter³

et al. 2007

BT Technol J

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“…One approach is to store tap sets of tap coefficients in the EC, one for each of two relative transmitreceive phases [37], with lead-lag sampling [33] used to adapt both phases. Another method which increases the computational overhead is to estimate the coefficients at the new sampling phase using a gradient estimation technique [38], [39].…”

Section: B Pll Timing Recoverymentioning

confidence: 99%

Design Issues in the ISDN U-Interface Transceiver

Messerschmitt

1986

IEEE J. Select. Areas Commun.

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Abstract-The design challenges faced in the integrated circuit realization of the basic customer access U-interface transceiver at 144 kbits/s in the integrated services digital network (ISDN) are summarized. Given the cost and performance objectives, thisrepresents a very challenging design problem from an algorithmic and technology point of view. This survey paper describes the alternative design approaches concentrating on algorithmic issues as opposed to circuit design issues, in the context of the echo cancellation (EC) method of full duplex data transmission. Particular emphasis is given to the areas of echo cancellation, equalization, line code selection, and timing recovery.

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Clock sensitivity reduction in echo cancellers

Cited by 13 publications

References 0 publications

Frequency-domain echo canceller with phase adjustment

Frequency-domain echo canceller with phase adjustment

A long reach digital subscriber loop transceiver

Design Issues in the ISDN U-Interface Transceiver

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