Clock recovery circuit for optical packets

40 Gb/s all-optical packet clock recovery with ultrafast lock-in time and low inter-packet guardbands

“…Although the experimental data presented use a 2 7 -1 PRBS, the clock recovery circuit can be designed according to the requirements of the network traffic by tailoring the finesse of the Fabry-Perot filter. For instance, if a PRBS of 2 31 -1 is required, the filter should be designed to have a finesse of 80 [9]. In this case, the recovered clock packet would exhibit less than 150 ps lock-in time and a decay time of approximately 2 ns.…”

“…In this letter we demonstrate a 40 Gb/s all-optical packet-mode clock recovery circuit based on the concept presented in [9] extending the bit-rate and reporting better operational characteristics and more detailed performance evaluation. By fully exploiting the potential offered by this technique we show for the first time, instant 40 Gb/s clock extraction from short and closely-spaced packets using simple optical components that do not require complex and specialized fabrication techniques.…”

IST-LASAGNE: towards all-optical label swapping employing optical logic gates and optical flip-flops

“…The AOLS node requires timing extraction on a packet-by-packet basis and a packet arrival detection scheme. These functionalities are performed by a clock recovery circuit [12] and a single-pulse generator. The former is placed at the beginning of the router and is capable of handling high-bit-rate burst mode optical packets.…”

“…In contrast to previously reported optical clock recovery circuits [14]- [16] comprising of high-Q cavities, the approach proposed here uses a low-Q passive filter in combination with a power-limiting optical gate to achieve instant locking and low clock persistence time, as described in [12]. Exploiting the memory effect of such a low-Q comb-generating filter, packet-to-packet processing is achievable due to the short impulse response of the filter.…”

“…Although the experimental data presented use a 2 7 − 1 PRBS, the clock recovery circuit can be designed according to the requirements of the network traffic by tailoring the finesse of the FPF. For instance, if a PRBS of 2 31 − 1 is required, the filter should be designed to have a finesse of 80 [12]. In this case, the recovered clock packet would exhibit less than 150 ps lock-in time and a decay time of approximately 2 ns.…”