Clock jitter estimation and suppression in OFDM systems employing bandpass ΣΔ ADC

Abstract

In this paper, we analyze the effect of clock jitter on the performance of OFDM-based systems applying digital IF architecture. A bandpass ΣΔ ADC is used for the analog to digital conversion process. An accurate and realistic model of the clock jitter in bandpass ΣΔ ADC is implemented. Results from this paper show that clock jitter severely degrades OFDM system performance by introducing both phase and waveform noise. It is shown that for the case of sampling at IF stage, the effect of waveform noise is quite small and negligible compared to the phase noise effect. Therefore, an estimation and compensation method based on the existing phase noise compensation method is proposed for alleviating the effect of clock jitter. Simulation results are presented, showing the significant performance gain of our proposed algorithm, providing a new and innovative way of dealing with the clock jitter problem of bandpass A/D conversion in OFDM systems.Index Terms -Sigma-delta modulators, analog-to-digital conversion, clock jitter, signal-to-noise ratio.978-1-4244-3696-5/09/$25.00

On-board signal predistortion for digital transparent satellites

“…The constraints are the one derived by replacing (9) in (7), and the variables are γ and δ. 3) LUT implementation of (3) on a DTP.…”

“…The analogto-digital converter (ADC) introduces three main types of noise: quantization noise (QN), clock jitter, and thermal noise [8]. QN can be mitigated by using a sigma-delta ADC [9] so that the residual noise can be modeled jointly with the thermal noise as zero-mean complex additive white Gaussian noise (AWGN). On the other hand, the clock jitter cannot be easily removed since its power spectral density (PSD) occupies the signal band [9].…”

“…QN can be mitigated by using a sigma-delta ADC [9] so that the residual noise can be modeled jointly with the thermal noise as zero-mean complex additive white Gaussian noise (AWGN). On the other hand, the clock jitter cannot be easily removed since its power spectral density (PSD) occupies the signal band [9]. Clock jitter is caused by phase noise affecting the clock oscillator of the ADC and generates a nonuniform sampling of the input signal.…”