Clock jitter and quantizer metastability in continuous-time delta-sigma modulators

Abstract

The performance of continuous-time (CT) delta-sigma modulators (16M's) suffers more severely from time jitter in the quantizer clock than discrete-time designs. Clock jitter adds a random phase modulation to the modulator feedback signal, which whitens the quantization noise in the band of interest and hence degrades converter resolution. Even with a perfectly uniform sampling clock, a similar whitening can be caused by metastability in the quantizer: a real quantizer has finite regeneration gain, and thus, quantizer inputs near zero take longer to resolve. This paper quantifies the performance lost due to clock jitter in a practical integrated CT 16M clocked with an on-chip voltage-controlled oscillator. It also characterizes metastability in a practical integrated quantizer using the quantizer output zero-crossing time and rise time as a function of both quantizer input voltage and the slope of the input voltage at the sampling instant, and predicts the maximum-achievable performance of a practical CT 16M given jitter and metastability constraints.

Microgyroscope control system using a high-order band-pass continuous-time sigma-delta modulator

“…However, this noise floor is about 10 dB higher. This degradation is likely to be due to the excess loop delay and clock jitter [19,21]. Measured voltage waveforms on the detection electrodes are shown in Fig.…”

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

“…We follow the literature of clock jitter in the context of CTDSM and focus on jitter noise reduction techniques in case of Independent Clock Jitter (ICJ) [6]. Suppose the ideal sampling period of a clock is T S .…”

“…where a n is jitter of rising/falling edge of the clock and is typically modeled as i.i.d (independent and identically distributed) Gaussian noise [6]. Its standard deviation is denoted as σ CLK J in this paper.…”

“…However, CTDSM have a few drawbacks, such as performance degradation due to excess loop delay [2], time-constant variation [3,4] and clock jitter effects [5,6]. Excess loop delay may be solved by either return-to-zero DAC feedback techniques [2], or by intentionally delaying the modulator output and adding compensation paths around the modulator loop filter [2,4].…”

Less jitter sensitive NTF design for NRZ multi-bit continuous-time Delta-Sigma modulators

“…Since the time-domain simulation of the jitter is very time-consuming, so it is beneficial to find analytic methods to predict the jitter effects [1,2]. The analytic approaches prove that the jitter induced noise of the modulator depends on both the input signal characteristics and the NTF of the modulator [3,4].…”