Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

Bezati, Endri; Casale-Brunet, Simone; Mattavelli, Marco; Janneck, Jörn W.

doi:10.1109/tcad.2016.2597215

Cited by 19 publications

(20 citation statements)

References 9 publications

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“…Present clock gating applied to a group of flip-flops, and the entire procedure is preceded by a detailed analysis of the activity of the blocks. The authors of [26] also show a clock-gating strategy that is successfully applied to dataflow designs based on streaming processing and implement it in FPGA structures. [27] deals with FPGA implementations of embedded systems as well, but the authors primarily attend to the power gating that allows dynamically controlling the power supply of the utilized modules.…”

Section: Related Workmentioning

confidence: 99%

“…Making a simple comparison with the solutions presented in other works is difficult from this point of view, because either those works were implemented on commercial architectures or they dealt with dedicated applications. Table 5 contains a comparison with the research presented in [26]. That work was also implemented on the same FPGA chip, a Xilinx Virtex 7, and the authors of [26] also used the gating method for energy reduction.…”

Section: Quantitative Analysis-the Maximum Processed Tasksmentioning

confidence: 99%

“…Table 5 contains a comparison with the research presented in [26]. That work was also implemented on the same FPGA chip, a Xilinx Virtex 7, and the authors of [26] also used the gating method for energy reduction. The percentage resource consumption and the percentage energy reduction using the gating technique were compared.…”

Section: Quantitative Analysis-the Maximum Processed Tasksmentioning

confidence: 99%

See 2 more Smart Citations

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Antolak

Pułka

2022

Applied Sciences

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The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing is proposed. The presented solution uses thread-interleaving mechanisms that allow avoiding hazards and minimizing unpredictability. The proposed architecture is compared with the classical solutions consisting of many processors and based on the scheme using one processor per single task. Energy-efficient task mapping is analyzed and a design methodology, based on minimizing the number of active and utilized resources, is proposed. New techniques for energy optimization are proposed, mainly, clock gating and switching-resources blocking. The authors investigate two main factors of the system: setting the processing frequency, and gating techniques; the latter are used under the assumption that the system meets the requirements of time predictability. The energy consumed by the system is reduced. Theoretical considerations are verified by many experiments of the system's implementation in an FPGA structure. The set of tasks tested consists of programs that implement Mälardalen WCET benchmark algorithms. The tested scenarios are divided into periodic and non-periodic execution schemes. The obtained results show that it is possible to reduce the dynamic energy consumed by real-time applications' meeting their other requirements.

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Section: Related Workmentioning

confidence: 99%

Section: Quantitative Analysis-the Maximum Processed Tasksmentioning

confidence: 99%

Section: Quantitative Analysis-the Maximum Processed Tasksmentioning

confidence: 99%

See 1 more Smart Citation

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Antolak

Pułka

2022

Applied Sciences

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“…To overcome this issue, MPEG-RVC provides a high level specification formalism, based on RVC-CAL that is a subset [8] of the CAL Actor Language (CAL) normalized as a part of the RVC standard 1 , constituting a starting point model for the direct software and hardware synthesis. Basically, RVC does not define a codec, but provides a way to describe codecs in a modular way (combining together Functional Units, FUs, from the modular Video Tool Library, VTL), along with a set of instruments to facilitate their analysis, customization, implementation and optimization [51,31,36,7,46,11,43,20,10,6,61]. Low level details of C/C++ codec implementations are abstracted away by describing a codec as an "abstract" RVC-CAL network of actors taken from the standard library.…”

Section: Reconfigurable Video Codingmentioning

confidence: 99%

Reconfigurable and approximate computing for video coding

Palumbo

2019

VLSI Architectures for Future Video Coding

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Systems perception capabilities are fundamental to make modern interconnected systems smart and, in this context, video coding is certainly a key technology. Video coding standards have been traditionally based on monolithic specifications coupled to a fixed set of profiles, capable of implementing different sub-set of functionalities of the given reference standard. Standards and profiles typically offer different features and enable different trade-offs that make them suitable for different applications and scenarios. Nevertheless, keeping the pace with constantly evolving scenarios and user's needs, for example in terms of offered quality or consumed power, is not that simple, and has led to continuous releases/updates of standards and profiles.Ideally designers should be allowed, at design-time, to select and combine coding tools and profiles to optimally match the given requirements, while guaranteeing that customized applications are still interoperable. Nevertheless, monolithic specifications tend to hide parallelism and the dataflow nature of video coding algorithms that, on the contrary, can be successfully exploited to guarantee efficient implementations and to play with different trade-offs [8].To address these issues, related to codecs design and customization, designers have been called to conceive efficient design-time methodologies

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“…Probably great benefits can be obtained by minimizing expected energy consumption at the system level. For example, we have found that it is possible to design the architecture with the possibility of involving elements responsible for power gating [20][21][22] of individual elements, or the clock gating [23][24][25]. Also, while reviewing methods to reduce energy consumption, the method of local voltage reduction was considered.…”

Section: Introductionmentioning

confidence: 99%

Low Power QC-LDPC Decoder Based on Token Ring Architecture

2020

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The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

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Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

Cited by 19 publications

References 9 publications

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Reconfigurable and approximate computing for video coding

Low Power QC-LDPC Decoder Based on Token Ring Architecture

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