Clock Gating Implementation on commercial Field Programmable Gate Array (FPGA)

Tan, Beng-Liong; Lee, Wai-Kong; Mok, Kai-Ming; Goh, Hock Guan

doi:10.1109/iceese.2018.8703530

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Cited by 4 publications

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“…For many years clock gating technique has been widely used as dominant power reduction technique in processor design by researchers as well as by industries. Recently this technique is even used in the soft-core processor implementation on Artix-7 FPGA [10].…”

Section: Clock Gatingmentioning

confidence: 99%

Low Power VLSI Design Techniques: A Review

Raut¹,

Chitre²,

Deshmukh³

et al. 2021

JUSST

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Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

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Section: Clock Gatingmentioning

confidence: 99%