This paper discusses a novel clock gat optimized for high performance and low po conventional CGC is analyzed along with o implementations of the CGC that have p proposed. The new CGC topology is compared to the topologies previously intro of dynamic clock power, leakage, area and ti
KeywordsClock gating cell, clock gater, local cl power design, clock gating.978-1-4799-1314-5/13/$31.00 ©2013 IEEE