Clock gating effectiveness metrics: Applications to power optimization

Srinivas, Jithendra; Rao, Madhusudan; Jairam, S.; Udayakumar, H.; Rao, J.

doi:10.1109/isqed.2009.4810342

Cited by 7 publications

(7 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…A thorough study of this matter is presented in [12]. A thorough study of this matter is presented in [12].…”

Section: Metricsmentioning

confidence: 99%

“…Note that in the equation of Figure 1(d), CGE refers to the weighted CGE, meaning that it is multiplied by the number of Flip-Flop (FF) in that clock domain. CG metrics description: (a) clock gating efficiency (CGE), (b) data-aware clock gating efficiency (DAGE), (c) correlated cluster gating efficiency (CCGE), and (d) energy-aware gating efficiency (EAGE) (adopted by [12]). CG metrics description: (a) clock gating efficiency (CGE), (b) data-aware clock gating efficiency (DAGE), (c) correlated cluster gating efficiency (CCGE), and (d) energy-aware gating efficiency (EAGE) (adopted by [12]).…”

Section: Metricsmentioning

confidence: 99%

“…In order to quantify and qualify the advantages and gains of CG optimization methods in a formalized way, it is essential to provide some metrics. A thorough study of this matter is presented in [12]. More specifically, four metrics are proposed and analyzed.…”

Section: Metricsmentioning

confidence: 99%

“…Figure 1. CG metrics description: (a) clock gating efficiency (CGE), (b) data-aware clock gating efficiency (DAGE), (c) correlated cluster gating efficiency (CCGE), and (d) energy-aware gating efficiency (EAGE) (adopted by [12]).…”

Section: Metricsmentioning

confidence: 99%

“…Srinivas et al [12] provide pseudo-code describing how these metrics can be calculated from the back end or synthesis EDA tools. Figure 1 depicts these metrics with a simplified example circuit and provides the equations that describe them.…”

Section: Metricsmentioning

confidence: 99%

See 4 more Smart Citations

Clock gating methodologies and tools: a survey

Pouiklis

2015

Circuit Theory & Apps

View full text Add to dashboard Cite

Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Figure 3. Basic CG structure. A clock input and a CG function provide the Clk and En signals to the ICG (integrated CG), which generates the gated clock used by the registers. CLOCK GATING METHODOLOGIES AND TOOLS: A SURVEY 801consumption is getting higher on the priorities and risks, during specifications and requirements definition, meaning that power saving exploration needs to be exhaustive. Thus, the research space and tool development for CG applications and optimizations remain as relevant as ever. 816G. POUIKLIS AND G. CH. SIRAKOULIS

show abstract

“…A thorough study of this matter is presented in [12]. A thorough study of this matter is presented in [12].…”

Section: Metricsmentioning

confidence: 99%

Section: Metricsmentioning

confidence: 99%

Section: Metricsmentioning

confidence: 99%

Section: Metricsmentioning

confidence: 99%

Section: Metricsmentioning

confidence: 99%