Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor

Melikyan, Vazgen; Babayan, E.; Melikyan, A. O.; Babayan, Davit; Petrosyan, Poghos; Mkrtchyan, E.

doi:10.1109/ewdts.2015.7493159

Cited by 7 publications

(1 citation statement)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Low-power design techniques and methodologies have been widely reported, each taking place at a very specific stage of the design flow (register transfer level (RTL), logical synthesis or physical synthesis). Examples of such methodologies include dynamic voltage and frequency scaling (DVFS) [2], parallel architecture [3], clock gating [4], and power gating [5].…”

Section: Introductionmentioning

confidence: 99%

Evaluating the Impact of Max Transition Constraint Variations on Power Reduction Capabilities in Cell-Based Designs

Chentouf¹,

Ismaili

2017

JLPEA

View full text Add to dashboard Cite

Abstract:Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet the power requirement. In this paper, we will evaluate, independently from the library file, the impact of redefining the max transition constraint (MTC) before the power optimization phase, and we will study the impact of over-constraining or under-constraining a design on power in order to find the best trade-off between design constraining and power optimization. Experimental results showed that power optimization depends on the applied MTC and that the MTC value corresponding to the best power reduction results is different from the default MTC. By using a new MTC definition method on several designs, we found that the power gain between the default methodology and the new one reaches 2.34%.

show abstract