Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology

Hansen, D. L.; Miller, Eric J.; KleinOsowski, A.J.; Kohnen, K.; Le, Anthony; Wong, Daniel Fu Keung; Amador, K.; Baze, M.P.; DeSalvo, D.; Dooley, M.; Gerst, K.; Hughlock, B.W.; Jeppson, B.; Jobe, R.D.; Nardi, D.; Ojalvo, I.; Rasmussen, B.; Sunderland, D.A.; Truong, John; Yoo, Moon-Hyun; Zayas, E.

doi:10.1109/tns.2009.2031972

Cited by 33 publications

(8 citation statements)

References 20 publications

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“…Because of the special redundancy design, TMR technique is usually considered relatively immune to direct upset in storage element showing orders of magnitude difference in SEU cross-section when compared to DFF. In [11], TMRFF fabricated in the 90nm bulk CMOS process shows two orders of magnitude harder than standard DFF, while in this work TMRFF results in only 90% decrease in the SEU cross-section. This weakened advantage can be contributed to the increased charge sharing with technology scaling.…”

Section: Direct Upsetmentioning

confidence: 63%

“…Neutron experiment performed in static mode show that TMRFF has decreased SEU improvement with technology scaling [9]. In dynamic mode, single event transient (SET) in combinational logic can be latched into hardened structures and corrupt the stored value [10][11][12][13], resulting in reduced SEU performance of the hardened elements. Recently, experiments on flip-flops without any additional inserted combinational logic demonstrate that SETs generated in the latches can also cause SEUs [14,15].…”

Section: Introductionmentioning

confidence: 99%

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Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Chen

2014

Sci. China Inf. Sci.

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Heavy ion experiments were performed on D flip-flop (DFF) and TMR flip-flop (TMRFF) fabricated in a 65-nm bulk CMOS process. The experiment results show that TMRFF has about 92% decrease in SEU crosssection compared to the standard DFF design in static test mode. In dynamic test mode, TMRFF shows much stronger frequency dependency than the DFF design, which reduces its advantage over DFF at higher operation frequency. At 160 MHz, the TMRFF is only 3.2× harder than the standard DFF. Such small improvement in the SEU performance of the TMR design may warrant reconsideration for its use in hardening design.

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Section: Direct Upsetmentioning

confidence: 63%

Section: Introductionmentioning

confidence: 99%

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Chen

2014

Sci. China Inf. Sci.

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“…Some novel RHBD FF designs are proposed to encounter this emerging threat [29,30]. Errors due to glitches in global control line such as clock/SET/REST line are also being recognized [31,32]. All of these new threats make device/component/system design much more complicated and difficult.…”

Section: Revisions Needed For Jesd89amentioning

confidence: 99%

Novel SER standards: Backgrounds and methodologies

Ibe

Shimbo

Toba

et al. 2010

2010 IEEE International Conference on Integrated Circuit Design and Technology

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Standard methods to quantify SER susceptibility in memory devices have been established during 2000-2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.

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“…As shown in Figure 1, a master-slave D flip-flop (DFF) consists of transmission gates and cross-coupled storage nodes. Except for direct upset at storage nodes (direct upset, for short) of this flip-flop, there are also indirect upset, that is, SEU can be caused by single event transient (SET) in non-storage nodes of a flip-flop [11][12][13][14]. The SET in transmission gate [11] and SET in clock signal [14] is also a possible cause of SEU.…”

Section: Introductionmentioning

confidence: 99%

“…Except for direct upset at storage nodes (direct upset, for short) of this flip-flop, there are also indirect upset, that is, SEU can be caused by single event transient (SET) in non-storage nodes of a flip-flop [11][12][13][14]. The SET in transmission gate [11] and SET in clock signal [14] is also a possible cause of SEU. What is more, in nanometer technology, multi-node charge collection may occur in flip-flop data input circuit and clock signal of a flip-flop simultaneously, and then bring about two single event transients (SET) in flip-flop data input circuit and clock signal simultaneously.…”

Section: Introductionmentioning

confidence: 99%

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

Huang

Chen

2016

Sci. China Inf. Sci.

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Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications. As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure, and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.Keywords single event upset (SEU), single event double transient (SEDT), SEDT-induced SEU, parasitic bipolar effect (PBE), charge sharing CitationHuang P C, Chen S M, Chen J J. Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology. Sci China Inf Sci,

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Clock, Flip-Flop, and Combinatorial Logic Contributions to the SEU Cross Section in 90 nm ASIC Technology

Cited by 33 publications

References 20 publications

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Novel SER standards: Backgrounds and methodologies

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology

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