Cleave Engineered Layer Transfer using Porous Silicon

Joshi, Monali; Hayashi, S.; Hu, Sun; Goorsky, Mark S.

doi:10.1149/1.2982877

Cited by 4 publications

(3 citation statements)

References 23 publications

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“…From this information, the interplanar distances are calculated for the out-of-plane (111) to be 3.394 Å and in-plane (110) to be 4.151 Å, which corresponds to a substantial 0.17% out-of-plane strain and a smaller 0.029% in-plane strain compared to cubic InP. Increases in lattice parameter have also been reported for other nanowires 37 and for porous silicon, 38 although the present study is the first to independently determine the in-plane and out-of-plane strain values for epitaxial InP nanowires. The origin for the lattice expansion is not known; thermal expansion coefficients, slight nonstoichiometry, and the effect of adsorbed surface species may all play a role.…”

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confidence: 87%

Self-Catalyzed Epitaxial Growth of Vertical Indium Phosphide Nanowires on Silicon

et al. 2009

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Vertical indium phosphide nanowires have been grown epitaxially on silicon (111) by metalorganic vapor-phase epitaxy. Liquid indium droplets were formed in situ and used to catalyze deposition. For growth at 350 degrees C, about 70% of the wires were vertical, while the remaining ones were distributed in the 3 other <111> directions. The vertical fraction, growth rate, and tapering of the wires increased with temperature and V/III ratio. At 370 degrees C and V/III equal to 200, 100% of the wires were vertical with a density of approximately 1.0 x 10(9) cm(-2) and average dimensions of 3.9 mum in length, 45 nm in base width, and 15 nm in tip width. X-ray diffraction and transmission electron microscopy revealed that the wires were single-crystal zinc blende, although they contained a high density of rotational twins perpendicular to the <111> growth direction. The room temperature photoluminescence spectrum exhibited one peak centered at 912 +/- 10 nm with a FWHM of approximately 60 nm.

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confidence: 87%

Self-Catalyzed Epitaxial Growth of Vertical Indium Phosphide Nanowires on Silicon

et al. 2009

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“…Using porous silicon/Si wafers in conjunction with wafer bonding and hydrogen exfoliation processes may bypass the limitation to homoepitaxial applications to create transfer-capable monolithic heterostructures. 7,8 A variety of composite semiconductor structures have been produced [9][10][11][12][13][14][15][16][17][18][19] using wafer bonding and hydrogen exfoliation techniques; this study focuses on the demonstrating the compatibility of porous silicon films with these processes for use in layer transfer applications.…”

Section: Introductionmentioning

confidence: 99%

Porous Silicon Films for Thin Film Layer Transfer Applications and Wafer Bonding

Joshi¹,

Hu²,

Goorsky³

2010

ECS Trans.

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Porous silicon films were fabricated from p+-Si (0.001-0.005 Ω cm) for their applicability to wafer bonding and layer transfer. Wafer bonding of porous silicon surfaces using silicon nitride interlayers was demonstrated, without the use of high temperature annealing. Conditions for producing porous silicon films compatible with both a) bonding surface requirements and b) layer transfer mechanical requirements were investigated. Nanoindentation showed quadratic dependence of Young's Modulus on relative density; films with mid-range Young's moduli were selected for layer transfer applications. Microstructural changes in annealed porous silicon films were studied using scanning electron microscopy and high resolution x-ray diffraction. Coarsening was observed at temperatures as low as 300 °C, the films remained pseudomorphic after annealing at all temperatures. After subsequent higher temperature annealing, mechanical fracture of the bonded stack occurred through the porous layer. The fracture mechanism for these structures is proposed.

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“…Using porous silicon/Si wafers in conjunction with wafer bonding and hydrogen exfoliation processes may bypass the limitation to homoepitaxial applications to create transfer-capable monolithic heterostructures. 7,8 A variety of composite semiconductor structures has been produced [9][10][11][12][13][14][15][16][17][18][19] using wafer bonding and hydrogen exfoliation techniques; this study focuses on demonstrating the compatibility of porous silicon films with these processes for use in layer transfer applications.…”

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confidence: 99%

Low Temperature Processing of Porous Silicon Films for Wafer Bonding-Based Thin-Film Layer Transfer Applications

Joshi

Goorsky

2010

J. Electrochem. Soc.

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Porous silicon films were fabricated from p + -Si ͑0.001-0.005 ⍀ cm͒ wafers and characterized for their applicability to wafer bonding and layer transfer schemes. Conditions for producing porous silicon films compatible with both ͑i͒ wafer bonding surface smoothness requirements and ͑ii͒ layer transfer mechanical requirements were investigated. Nanoindentation of various films showed the quadratic dependence of Young's modulus on relative density. High porosity films ͑Ͼ90%͒ exhibited prohibitively high surface roughness values for wafer bonding applications, while wafers with lower porosity produced surfaces that were sufficiently smooth; films with midrange Young's modulus were selected for layer transfer applications. Demonstration of wafer bonding of porous silicon surfaces using silicon nitride interlayers was shown without the use of a high temperature anneal step to densify the porous surface or chemical mechanical polishing. Coarsening of the porous structure was observed at temperatures as low as 300°C, and the porous films remained pseudomorphic after annealing at all temperatures, as high as 900°C. Strong bonds were formed at the silicon nitride interfaces after low temperature annealing. After higher temperature annealing, mechanical fracture of the bonded stack occurred in the porous film parallel to the wafer bond interface. A fracture mechanism for these structures is proposed.Thin-film layer transfer represents a promising technique to increase versatility in the fabrication of complex semiconductor devices. Interest in layer transfer techniques to fabricate engineered substrates was largely sparked by the desire for silicon-on-insulator structures. One such technique, ELTRAN ͑Epitaxial Layer TRANsfer͒, 1-5 incorporated a silicon wafer that was electrochemically etched to produce a porous film at the surface; after annealing in a hydrogen atmosphere to sinter pores at the surface to produce a thin, fully dense surface layer, this film is subsequently used as a template for silicon homoepitaxy. This structure is then bonded via silicon dioxide interlayers to a silicon handle wafer, and transfer of the epitaxial Si layer is achieved by use of a high pressure water jet to fracture the stack at the weakest layer, namely the porous silicon. 1,5 The use of porous silicon as an imbedded mechanically weak layer leads to large area yield layer transfer; however, utilization of this and similar methods such as the porous Si process ͑PSI͒ 6 is limited to the transfer of silicon homoepitaxial or pseudomorphic layers.Using porous silicon/Si wafers in conjunction with wafer bonding and hydrogen exfoliation processes may bypass the limitation to homoepitaxial applications to create transfer-capable monolithic heterostructures. 7,8 A variety of composite semiconductor structures has been produced 9-19 using wafer bonding and hydrogen exfoliation techniques; this study focuses on demonstrating the compatibility of porous silicon films with these processes for use in layer transfer applications.Previous studies cond...

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Cleave Engineered Layer Transfer using Porous Silicon

Cited by 4 publications

References 23 publications

Self-Catalyzed Epitaxial Growth of Vertical Indium Phosphide Nanowires on Silicon

Self-Catalyzed Epitaxial Growth of Vertical Indium Phosphide Nanowires on Silicon

Porous Silicon Films for Thin Film Layer Transfer Applications and Wafer Bonding

Low Temperature Processing of Porous Silicon Films for Wafer Bonding-Based Thin-Film Layer Transfer Applications

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