Cleanliness Management in Advanced Microelectronic

Abstract

After technical results presented the last two years and new results on volatile contamination, this paper reviews the contamination management in advanced microelectronic and proposes rules for advanced Integrated Circuits (IC) manufacturing. The competitiveness of a production line is insured only if right contamination management rules are applied. These rules must allow a fast introduction of disruptive technologies while keeping as low as possible associated costs: processing on shared equipments, determination of acceptable levels of contamination with a good understanding of their detrimental impact on devices, knowledge on contamination dissemination mechanisms. Moreover, a control of contamination using appropriate cleanings and metrologies is mandatory.

Metal Removal Efficiency in Deep Submicron Trenches by Wet Chemicals

“…Most easily observable phenomenon is an abnormal catalytic growth of CVD (Chemical Vapor Deposition) films [7] [8]. Silicon nitride whiskers or poly silicon over growth are locally found on accidentally contaminated wafers (figures 2 and 3) [9]. A deep focus is hereby made on even lower metal traces, at levels lower than 1E+8at/cm², known to generate white pixels defects for image sensors [10] [11] (figure 4).…”

Impact of Metallic Contamination on Si: Shortloop Issues

“…Thus, considering also the "conventional" contaminants related to equipments, fluids and human activity, up to 50 metallic elements might have to be considered in advanced microelectronics. The works published in 2005 by C.Bigot et al (1), and in 2006 by Y.Borde et al (2) deal with, on one hand, the classification of each metallic element according to their properties toward Si and SiO 2 (first group: metallic elements remaining inside the oxide; second group: metallic elements forming precipitates at the interface Si/SiO2; third group: metallic elements diffusing inside the Silicon), and on the other hand, their dangerousness towards Si or/and SiO 2 (see Fig. 1).…”