Classic and alternative methods of p-type doping 4H-SiC for integrated lateral devices

Lazar, Mihai; Carole, Davy; Raynaud, Christophe; Ferro, Gabriel; Sejil, Selsabil; Laariedh, Farah; Brylinski, Christian; Planson, Dominique; Morel, Hervé

doi:10.1109/smicnd.2015.7355190

Cited by 5 publications

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References 17 publications

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“…One of the peculiarities of silicon carbide is that due to the high Si-C bond strength, the diffusion coefficients of dopant species in the material are extremely low, even at very high temperatures (above 1500 °C). Figure 1 reports an Arrhenius plot of the diffusion coefficients for the major dopants in SiC and Si [ 1 , 13 , 22 , 23 , 24 , 25 ]. As can be seen, the diffusion coefficients of dopant impurities in SiC are in the order of 10 −17 –10 −15 cm 2 s −1 at about 1800 °C, i.e., several orders of magnitude lower than those of Si dopants (10 −14 –10 −13 cm 2 s −1 ) at 1000 °C.…”

Section: Background On Selective Doping In Sic Power Devicesmentioning

confidence: 99%

“… Arrhenius dependence of the diffusion coefficients of different dopant species in silicon carbide (continuous lines) and silicon (dashed lines). The data are taken from [ 1 , 13 , 22 , 23 , 24 , 25 ]. …”

Section: Figurementioning

confidence: 99%

“…In this context, many comprehensive regular and review papers have discussed the most relevant implications of ion implantation of SiC, e.g., crystal damage, amorphization and recrystallization, doping, annealing, contact formation, etc. [ 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 ].…”

Section: Introductionmentioning

confidence: 99%

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Selective Doping in Silicon Carbide Power Devices

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Silicon carbide (SiC) is the most mature wide band-gap semiconductor and is currently employed for the fabrication of high-efficiency power electronic devices, such as diodes and transistors. In this context, selective doping is one of the key processes needed for the fabrication of these devices. This paper concisely reviews the main selective doping techniques for SiC power devices technology. In particular, due to the low diffusivity of the main impurities in SiC, ion implantation is the method of choice to achieve selective doping of the material. Hence, most of this work is dedicated to illustrating the main features of n-type and p-type ion-implantation doping of SiC and discussing the related issues. As an example, one of the main features of implantation doping is the need for post-implantation annealing processes at high temperatures (above 1500 °C) for electrical activation, thus having a notable morphological and structural impact on the material and, hence, on some device parameters. In this respect, some specific examples elucidating the relevant implications on devices’ performances are reported in the paper. Finally, a short overview of recently developed non-conventional doping and annealing techniques is also provided, although these techniques are still far from being applied in large-scale devices’ manufacturing.

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Section: Background On Selective Doping In Sic Power Devicesmentioning

confidence: 99%

Section: Figurementioning

confidence: 99%

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Selective Doping in Silicon Carbide Power Devices

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“…A implantação de dopantes em substratos de Si por meio do aquecimento é o método mais utilizado atualmente, porém para substratos de SiC a dopagem por aquecimento em pontos específicos (por exemplo o contato N+ da fonte), só é possível por meio da implantação iônica [92] [93]. No entanto, há muito mais preocupações sobre o processo de dopagem, uma vez que o carbono também tende a competir com os dopantes pela mesma posição no cristal [42].…”

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Análise das propriedades básicas do sic VDMOSFET (WBG) para aplicações de tração automotiva

Feitosa¹

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The vehicular fleet around the world is going through an enormous transition in its energetic matrix, mostly because governments around the globe are concerned about pollution. This paper focus on the research of Wide Band Gap (WBG) Silicon Carbide (SiC) Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOSFET), concerning to its use in electric vehicles, through manufacturer datasheet data and TCAD simulation analysis. Three main parameters were addressed: interface charge density, channel doping concentration density and gate to channel overlap/underlap. For each of the parameters, the IDS x VDS curves were traced for several values. Threshold voltage (Vth), maximum transconductance (max. gm) and subthreshold slope (S) were analyzed. This work describes in detail the device characteristics and mathematical models that are needed for TCAD simulation. This work shows the importance of power electronics for electric vehicles (EVs), what is the current and future EVs` need, and highlights the advantages that the SiC VDMOSFET presents. The analyzed data show that the threshold voltage and subthreshold slope increase with the increase on channel dopant concentration. As for the increase interface charge, it was observed that the threshold voltage decreases, and that the same occurs when there is a gate underlap. The maximum transconductance deteriorates with the increase in the channel doping concentration in greater level when compared with the maximum transconductance deterioration caused by the interface charge increase. However, gate underlap drastically deteriorates the maximum transconductance, and subthreshold slope increases as the gate underlap increases.

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“…On the one hand, high-energy ion implant induces a surface damage thus increasing surface roughness. Moreover, annealing at temperatures above ~1550 °C leads to Si evaporation from SiC wafer surface, thus also increases surface roughness [53]. The use of carbon capping layers is a suitable solution to prevent surface roughness caused during high temperature annealing.…”

Section: Activation Of Impuritiesmentioning

confidence: 99%

Design and process developments towards an optimal 6.5 kV SiC power MOSFET

Soler

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A sustainable future requires efficient power electronic converters at any stage of the electrical energy consumption. Silicon carbide (SiC) is one of the most technologically advanced wide bandgap semiconductors that can outperform silicon limits for power devices. SiC power MOSFETs are of the greatest interest since they are unipolar gate-controlled switches with high blocking voltage capability and reasonably low specific on-resistance. The focus of this thesis is on the design optimisation and process technology refinement towards the improvement of high-voltage SiC MOSFETs. Previous developments in our group were taken as a reference for this work. The results of this research allowed the fabrication of large-area SiC power MOSFETs with voltage ranges targeting 1.7 kV up to 6.5 kV. The inherent properties of SiC entail challenging technological solutions to successfully integrate a power MOSFET of such high-voltage capability. To ensure suitable blocking capability, different planar edge termination structures have been designed, optimised by TCAD simulation and implemented on PiN diodes. The termination schemes considered are single-zone JTE, FGRs and a novel RA-JTE structure combining JTE with rings. RA-JTE design, with the lowest sensitivity to fabrication process deviations and a lower consumed area, achieved more than 90% of the ideal breakdown voltage and suitable blocking capability up to 6.5 kV. The optimisations performed on the unit-cell of the SiC power MOSFET target both the layout design and the fabrication process. The optimisation has been performed by TCAD modelling and experimental evaluation of specific test structures. Several techniques to improve the performance of the fabricated devices have been considered: i) the use of an offset retrograde p-body profile to provide an adequate Vth value while preventing p-body punch-through, ii) a submicronic self-aligned channel definition, iii) a boron treatment to the gate oxide to improve channel mobility, iv) a discrete location of the p-contact to reduce cell-pitch, v) the use of a lower-doped-source (LDS) to improve reliability, vi) the optimisation of the JFET area, and vii) the integration of gate runners to improve the switching performance. As a result of these investigations, a full mask-set were designed and used for processing wafers of several voltage-class in different batches. All the fabrication steps have been carried out at IMB-CNM cleanroom. The electrical characterisation of large-area devices has evidenced an optimal Vth in the range of 5 V, a proper gate control, and a good blocking capability. We obtained relatively high specific on-resistance due to the large cell pitch dimensions required by IMB-CNM cleanroom design rules as well as a still low channel mobility. Fabricated SiC MOSFETs are capable of switching at high bus voltages (tested up to 80% of the rated voltage). Although, their switching performance is limited by internal gate resistance. Fabricated devices have shown better short-circuit capability (>15 µs) than existing commercial devices, mainly due to the cell design considerations. The evaluation of electrical performance evidenced the successful functionality of the fabricated VDMOS up to 6.5 kV and validates our new RA-JTE termination design. On the other hand, the novel boron doping treatment to the gate oxide clearly demonstrated to improve the on-resistance of our devices in all voltage classes without affecting breakdown and short-circuit capabilities. Nevertheless, it strongly compromises stability and reliability at temperatures above 100 °C. These results show that the MOS interface quality is still the major issue for the development of reliable SiC power MOSFETs. Finally, alternative SiC structures have also been investigated to take advantage of the SiC superior material properties. These include a SiC IGBT showing conductivity modulation, and a preliminary SiC CMOS cell able to operate at high temperatures. Un futur sostenible requereix convertidors electrònics d'alta potència eficients per totes les fases del consum d'energia elèctrica. El carbur de silici (SiC) és un dels semiconductors de banda prohibida ampla més avançats que permet superar els límits de silici en dispositius de potència. El gran interès en els MOSFETs de potència SiC recau en que són interruptors unipolars que presenten una alta capacitat de tensió de bloqueig i una resistència específica relativament baixa. L’objectiu d’aquesta tesi és la optimització del disseny i el perfeccionament de la tecnologia de processos per a la millora dels MOSFETs d’alta tensió SiC tenint com a referencia els desenvolupaments previs realitzats pel grup. Els resultats d'aquesta investigació han permès la fabricació de MOSFETs de potència de SiC d’àrea gran amb capacitat de bloqueig des de 1,7 kV fins a 6,5 kV. Les inherents propietats del SiC requereixen solucions tecnològiques específiques per a integrar amb èxit un MOSFET de potència de tensió tan elevada. Per garantir una bona capacitat de bloqueig, s'han dissenyat diferents estructures de terminació planars, optimitzades per simulació i implementades sobre díodes PiN. Els esquemes de terminació considerats son JTE mono-zona, FGR i una nova estructura RA-JTE que combina una JTE amb anells flotants. La terminació RA-JTE, amb una menor sensibilitat a desviacions del procés de fabricació i menor àrea consumida, ha aconseguit més del 90% de la tensió ideal i bona capacitat de bloqueig per dispositius de fins a 6,5 kV. Les millores realitzades a la cel·la del MOSFET de SiC afecten tant al disseny com al procés de fabricació. L’optimització de la cel·la bàsica s’ha realitzat mitjançant simulacions TCAD i l’avaluació de dades experimentals mesurades en estructures de test específiques. Les tècniques aplicades per a la millora del rendiment dels MOSFETs de SiC inclouen: i) l’ús d’un perfil de dopatge retrògrad pel pou p per obtenir un valor de Vth adequada alhora que s'evita el punch-through del pou p, ii) canal auto-alineat de longitud sub-micrònica, iii) un tractament de bor a l'òxid de la porta per millorar la interfície, iv) la ubicació discreta del contacte p per reduir les dimensions de la cel·la, v) una regió de font menys dopada (LDS) per millorar la fiabilitat, vi) l’optimització de l’àrea JFET i vii) la integració de corredors de porta per reduir el temps de commutació. Com a resultat d'aquestes investigacions, un joc complet de màscares s’ha dissenyat i utilitzat per processar oblies de diferents rangs de tensió. Tots els processos de fabricació s’han realitzat a la sala blanca de l’IMB-CNM. La caracterització elèctrica dels MOSFETs d’àrea gran mostra una Vth en el rang de 5 V, control de la porta i bona capacitat de bloqueig. No obstant, la resistència específica és relativament alta a causa de les dimensions de cel·la i la baixa mobilitat al canal. Els MOSFETS de SiC fabricats commuten a altes tensions de bus, però el temps de transició està limitat per la resistència interna de porta. Els dispositius fabricats presenten una capacitat de curtcircuit (>15 µs) superior als dispositius comercials, principalment gràcies al disseny de la cel·la. L’anàlisi del comportament elèctric valida el funcionament satisfactori dels MOSFETs de SiC fabricats fins a 6,5 kV així com també el disseny de terminació RA-JTE. El nou tractament de bor a l’òxid de porta ha demostrat reduir la resistència dels VDMOS fabricats en totes les classes de tensió sense afectar a la capacitat de bloqueig i de curt-circuit, però en compromet l'estabilitat i la fiabilitat a més de 100 °C. Aquests resultats mostren que la qualitat de la interfície continua sent el punt clau per al desenvolupament de MOSFETs de potència fiables en SiC. Finalment, també s’han investigat estructures alternatives en SiC. Destaca la integració d’un IGBT...

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Classic and alternative methods of p-type doping 4H-SiC for integrated lateral devices

Cited by 5 publications

References 17 publications

Selective Doping in Silicon Carbide Power Devices

Selective Doping in Silicon Carbide Power Devices

Análise das propriedades básicas do sic VDMOSFET (WBG) para aplicações de tração automotiva

Design and process developments towards an optimal 6.5 kV SiC power MOSFET

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