Circularscan: a scan architecture for test cost reduction

Abstract

Scan-based designs are widely used to decrease the complexity of the test generation process; nonetheless, they increase test time and volume. A new scan architecture is proposed to reduce test time and volume while retaining the original scan input count. The proposed architecture allows the use of the captured response as a template for the next pattern with only the necessary bits of the captured response being updated while observing the full captured response. The theoretical and experimental analysis promises a substantial reduction in test cost for large circuits.

DCScan: A Power-Aware Scan Testing Architecture

“…Fig.1 (a) shows an example of a single scan chain with 9 scan cells and its test set. Scan cells ff 3 , ff 4 and ff 6 , ff 1 and ff 9 are compatible respectively. Scan cell ff 7 is NOT-compatible with ff 1 and ff 9 .…”

“…VirtualScan technology [2] reduces test cost by reducing the longest scan chain length in a full-scan circuit. CircularScan architecture [3] reduces test application time and test data volume drastically by using the captured response for the next *To whom correspondence should be addressed. This paper is supported in part by the National Natural Science Foundation of China (NSFC) under grant No.…”

“…There are many techniques [1][2][3] to reduce test application time. [1] effectively reduces test application time and test data volume for designs with multiple scan chains by using a reconfigurable switch to apply tests from a limited number of external inputs to a large number of internal scan chains.…”

Improving the Test of NoC-Based SoCs with Help of Compression Schemes

“…These don't care bits do not have to be stored into ATE but can be supplied on-chip in some other ways. LFSRs [7,8], Xor networks [9,10], ring generator [11], RAM [12,13], arithmetic units [14], and test pattern broadcasting among multiple scan chains [15][16][17] constitute a range of solutions for minimizing the number of data to be stored in the ATE and the number of visible test interfaces (scan chains in this case).…”

A Complete Logic BIST Technology with No Storage Requirement

“…The work in [12] addresses this problem by using a jumping logic for state transition such that the desired patterns can be generated effectively. Recently, the CircularScan method [13] modifies each scan chain to a circular scan chain and circularly shifts the captured response for each circular chain independently to construct the next pattern. In [14] the authors propose to connect some internal nets of the CUT to its inputs so as to provide the required logic values of the next pattern directly.…”