Circuits and devices for standalone large-scale integration (LSI) chips and Internet of Things (IoT) applications: a review

Sugiura, Takaya; Yamamura, Kenta; Watanabe, Yuta; Yamakiri, Shiun; Nakano, Nobuhiko

doi:10.1016/j.chip.2023.100048

Cited by 10 publications

(5 citation statements)

References 96 publications

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“…As they are designed on standard CMOS process and not specialized to design PV cells, there are a few restrictions for enhancing cell performances. 123 The simplest type is the single pnjunction formation on the front surface of LSI chips. 124 There is a report of on-chip back-contact PV cells that recorded 4.6% efficiency at infrared illumination.…”

Section: Novel Cellsmentioning

confidence: 99%

Review: Numerical simulation approaches of crystalline‐Si photovoltaics

Sugiura

Nakano

2023

Energy Science & Engineering

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This study reviews the current methods of numerical simulations for crystalline‐Si (c‐Si) photovoltaic (PV) cells. The increased demand for PV devices has led to significant improvements in the performance of solar cell devices. The main contribution comes from c‐Si solar cells, which constitute 90% of the industry. Numerical analysis is effective for predicting, developing, and optimizing cell performances as the cell structures become more complex and include several parameters. However, conventional methods cannot simulate improved device structures with complex configurations. Additional physics is necessary to evaluate these cell structures. This study introduces methods for evaluating these cell structures using physical modeling and highlights the latest examples of simulations of c‐Si solar cells.

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Section: Novel Cellsmentioning

confidence: 99%

Review: Numerical simulation approaches of crystalline‐Si photovoltaics

Sugiura

Nakano

2023

Energy Science & Engineering

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“…As illustrated in Fig. 5, a pn-junction can be used to form normal and shear stress sensors on standard CMOS chips [100] that enhance the Internet of Things (IoT) device functions.…”

Section: Applicationsmentioning

confidence: 99%

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

Sugiura

Matsuda

Nakano

2023

IEEE J. Electron Devices Soc.

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The field of piezoresistance has mainly advanced through experimental research; however, the improved accuracy of simulations and the emergence of new materials have increased the importance of simulations in this field. This review discusses the methods and current topics related to simulations of piezoresistive devices. Advancing simulation modeling will facilitate the computer-aided design of piezoresistive devices, and this review introduces the means of establishing these models by discussing the current studies on simulations and calculations in this field. Two simulation methods currently exist namely, device simulations and first-principles theoretical analysis. This review focuses on numerical simulation approaches for modeling of the piezoresistive effect using the multiphysics simulations of the mechanical and electrical behaviors of piezoresistive materials.

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“…T HE integration of energy harvesters with large-scaleintegration (LSI) chips for standalone operation is essential in the field of Internet of Things [1]. Energy harvesters, such as photovoltaic cells, thermoelectric devices, and piezoelectric resonators, are potential candidates for this integration.…”

Section: Introductionmentioning

confidence: 99%

Bulk Carrier Contaminations and Their Effects on MOSFETs Under Energy Harvesting Systems

Watanabe,

Sugiura,

Nakano

2024

IEEE J. Electron Devices Soc.

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Energy harvesters, such as photovoltaic cells, generate carriers in the deep substrate regions; these carriers can affect MOSFETs and deteriorate their performance or even cause malfunctioning. In this study, we discussed the effects of bulk carrier contamination on integrated MOSFETs in the context of energy-harvesting devices. We confirmed that the close integration of MOSFET circuits in a photovoltaic cell causes malfunctioning under strong light illumination. Moreover, numerical simulations revealed that PMOS is highly sensitive to carrier contamination as a forward pn-junction from the bulk-side storage carriers into the NWell region. Furthermore, increasing the distance from the illumination window was not an effective countermeasure, and alternative methods, such as the silicon-on-insulator substrate, n − -substrate, or NMOS logic, should be implemented for such large-scale integration.

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Circuits and devices for standalone large-scale integration (LSI) chips and Internet of Things (IoT) applications: a review

Cited by 10 publications

References 96 publications

Review: Numerical simulation approaches of crystalline‐Si photovoltaics

Review: Numerical simulation approaches of crystalline‐Si photovoltaics

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

Bulk Carrier Contaminations and Their Effects on MOSFETs Under Energy Harvesting Systems

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