Circuit extraction on a message-based multiprocessor

Tonkin, B.A.

doi:10.1109/dac.1990.114864

Cited by 7 publications

(3 citation statements)

References 13 publications

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“…Parallel processing is fast becoming an attractive solution to reduce the inordinate amount of time spent in VLSI circuit design. This has been recognized by several researchers in VLSI CAD as is evident in recent literature for cell placement [6,3,10], floor planning [11], circuit extraction [12,13], test generation and fault simulation [14,15,16], etc.…”

Section: An Overview Of the Propercad II Projectmentioning

confidence: 99%

An evaluation of parallel simulated annealing strategies with application to standard cell placement

Chandy

Kim

Ramkumar³

et al. 1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Simulated annealing, a methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm, and as such, numerous researchers have undertaken efforts to parallelize it. In this paper, we investigate three of these parallel simulated annealing strategies when applied to standard cell placement, specifically the TimberWolfSC placement tool. We have examined a parallel moves strategy, as well as two new approaches to parallel cell placement, multiple Markov chains and speculative computation. These algorithms have been implemented in ProperPLACE, our parallel cell placement application, as part of the ProperCAD II project. We have constructed ProperPLACE so that it is portable across a wide range of parallel architectures. Our parallel moves algorithm uses novel approaches to dynamic message sizing, message prioritization, and error control. We show that parallel moves and multiple Markov chains are effective approaches to parallel simulated annealing when applied to TimberWolfSC, yet, speculative computation is wholly inadequate.

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Section: An Overview Of the Propercad II Projectmentioning

confidence: 99%

An evaluation of parallel simulated annealing strategies with application to standard cell placement

Chandy

Kim

Ramkumar³

et al. 1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…Several sequential circuit extractors of varying speed and accuracy already exist [7,8,10,15,21,23]. Parallel algorithms for circuit extraction have also been recently proposed [3,4,14,25]. These algorithms perform parallel circuit extraction in several phases, including a data distribution phase, a geometric extraction phase, a merge phase, a device extraction phase and a parameter extraction phase.…”

Section: Vlsi Circuit Extractionmentioning

confidence: 99%

“…Parallel processing for CAD applications is becoming gradually recognized as a popular vehicle to support the increasing computing requirements of future CAD tools. Recent research on parallel CAD applications have been reported for a wide variety of applications such as placement [2,13,19,20], floor planning [11], circuit extraction [3,4,14,25], test generation and fault simulation [17], etc. Parallel processing for VLSI CAD has become a reality in industry as well.…”

Section: Introductionmentioning

confidence: 99%

ProperCAD: A portable object-oriented parallel environment for VLSI CAD

Ramkumar

Banerjee

1994

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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8a. NAME OF FUNDING/SPONSORING ORGANIZATION 7a 6b. OFFICE SYM80L (If applica bit) N/A 5. MONITORING ORGANIZATION REPORT NUMBER(S) 7a. NAME OF MONITORING ORGANIZATION NASA Semiconductor Research Corp 8b. OFFICE SYMBOL (If applica bl*) 7b. ADDRESS (C/ty, Sfata, a n d ZIP C o d *) Moffitt Field, CA 9. PROCUREMENT INSTRUMENT IDENTIFICATION NUMBER Research Triangle Park, NC 27709 8c ADDRESS (City, Stat*. a nd ZIP C od *) 10. SOURCE OF FUNDING NUMRPRÇ

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ProperTEST: a portable parallel test generator for sequential circuits

Ramkumar

Banerjee

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Circuit extraction on a message-based multiprocessor

Cited by 7 publications

References 13 publications

An evaluation of parallel simulated annealing strategies with application to standard cell placement

An evaluation of parallel simulated annealing strategies with application to standard cell placement

ProperCAD: A portable object-oriented parallel environment for VLSI CAD

ProperTEST: a portable parallel test generator for sequential circuits

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