Chlorine-enhanced thermal oxides growth and significant trap density reduction at SiO2/SiC interface by incorporation of phosphorus

Carrier Trap Density Reduction at SiO2/4H-Silicon Carbide Interface with Annealing Processes in Phosphoryl Chloride and Nitride Oxide Atmospheres

“…However, Okamoto et al observed that the trap state density near the conduction band edge is reduced by approximately one order of magnitude as compared with a dry-oxidized SiC reference, and it is almost constant for energies deeper in the bandgap. The present study is roughly concurrent with our previously reported findings [27]. This result is also consistent with the theoretical research of Kobayashi et al [58], which shows via DFT simulations that, at the upper band, close to the conduction band, carbon-related defects play a dominant role in the interface trap density profile [17,[59][60][61], and these can be reduced due to the creation of the −O 3 PCO 2 in the oxide film near the interface during POCl 3 treatment.…”

“…The oxygen–SiC reaction at this temperature is too slow for efficient SiO 2 formation in the timescale used in the experiment. However, it is worth mentioning that the SiC oxidation reaction in the POCl 3 ambient has been reported to have lower activation energy than in the dry oxygen [ 27 , 69 ].…”

“…It leads to a decrease in P concentration in the layer and, consequently, to a decrease in the positive charge accumulated in this layer during POCl 3 annealing. Formation of the PSG-like layer during POCl 3 annealing can be the most critical step in the application of such a layer to a gate dielectric in MOSFETs, which has been studied in the last decade [ 25 , 26 , 27 , 28 ]. Such considerations are mainly due to two reasons: (1) it was shown that introducing phosphorus can decrease the energy barrier for the Fowler–Nordheim current that dominates the conduction mechanism at the high electric field leading to the premature dielectric breakdown [ 56 ], and (2) a high concentration of phosphorus ions in the oxide film can lead to thermal instability of the device, as some of the ions in the oxide volume can be mobile under the strong electric fields present in the MOS device during its operation, modulating the device’s threshold voltage.…”

“…It is the thermal P diffusion process with trichlorophosphate (POCl 3 ) vapors, known in silicon technology. Some papers confirmed improved channel electron mobility in MOSFET, but the oxide film’s parameters changed after the thermal POCl 3 process [ 25 , 26 , 27 ]. Moreover, ions introduced into the oxide film can influence other MOSFET parameters, for example, oxide gate reliability such as dielectric strength, higher leakage at high fields, and thermal instability under high electric fields [ 28 ].…”

Bulletin of the Polish Academy of Sciences: Technical Sciences

“…This relationship is not linear in the whole Q it range. An increase in the Q it value from +1×10 11 cm −2 to +1×10 12 cm −2 results in the decrease of breakdown voltage from 2293 V to 2130 V, while the increase of the charge in the range from +1×10 12 cm −2 to +1×10 13 cm −2 results in the reduction of breakdown voltage from 2130 V to about 600 V. Real Q it charge values range from +1×10 11 cm −2 to even +1×10 12 cm −2 [21], therefore when designing the edge termination, the occurrence of a nonzero Q it value should be taken into account and the JTE region should be designed carefully to obtain the sensitivity of the breakdown voltage value on the surface charge density as low as possible.…”