Chips Classification for Suppressing Transient Current Imbalance of Parallel-Connected Silicon Carbide MOSFETs

Ke, Junji; Zhao, Zhibin; Sun, Peng; Huang, Huazhen; Abuogo, James; Cui, Xiang

doi:10.1109/tpel.2019.2934739

Cited by 37 publications

(15 citation statements)

References 21 publications

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“…The common mode current i Dc and the differential mode current i Dd are defined as Then substitute ( 17) into (16), and (16) can be simplified as…”

Section: Cs Mismatch Between Paralleled Devices With Cscmentioning

confidence: 99%

“…Furthermore, the short circuit failure of the SiC power module caused by the spread of threshold voltage was reported in [12]. In order to address the issues of the spread of device parameters, several methods have been reported [13][14][15][16][17][18]. An algorithm for calculation of de-rating factor for paralleled SiC MOSFETs was proposed in [13,14].…”

Section: Introductionmentioning

confidence: 99%

“…An algorithm for calculation of de-rating factor for paralleled SiC MOSFETs was proposed in [13,14]. A screening method based on transfer curves and clustering algorithm was developed to mitigate the current imbalance of paralleled SiC MOSFETs in [15,16]. Moreover, the active current balancing method [17,18] and the passive balancing method based on drive-source resistor and inductors [19] or coupled power-source inductors [20] were proposed to reduce the current imbalance due to the mismatches in threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

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Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices

Zhang

Peng

et al. 2022

IET Power Electronics

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This paper comprehensively investigates the current distribution behaviours of paralleled SiC MOSFET devices under the parasitic coupling between gate and power loops. Three types of connection that are commonly adopted in actual applications, comprising common source connection (CSC), Kelvin source connection (KSC) and hybrid source connection (HSC), are thoroughly discussed. The influence mechanism of mismatch in values for three parasitic inductances on current sharing during different switching periods is studied in theory. Simulations and experiments are also carried out and results are used to validate the theoretical analysis. Parasitic capacitance, common source and quasi common source parasitic inductance couplings are the three main coupling modes between gate loop and power loop in a circuit with paralleled SiC MOSFETs. The current imbalance is mainly due to the variation of gate-source voltage generated by the mismatch in the parasitic inductances through the three coupling paths. This paper aims to provide an insight into current sharing mechanism of paralleled devices with circuit parasitic mismatches. Influence of every parasitic inductance under each of the three coupling modes is investigated and recommendation made on choice of coupling mode and viable switching speed and current balance tradeoff that can be adopted in a practical system design.

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“…The common mode current i Dc and the differential mode current i Dd are defined as Then substitute ( 17) into (16), and (16) can be simplified as…”

Section: Cs Mismatch Between Paralleled Devices With Cscmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices

Zhang

Peng

et al. 2022

IET Power Electronics

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“…In [1,[24][25][26][27][28], novel screening methods are proposed, capable of discovering SiC MOS-FETs with almost identical technical characteristics, such as threshold voltage and transconductance, with the goal of achieving an equal current sharing without the necessity of a current balancing method. According to [11,29], the current unbalance, which is attributed to the PCB layout asymmetry, can be limited by suppressing the mismatches of the drain and power source parasitic inductances, resulting in a very close symmetrical layout.…”

Section: Introductionmentioning

confidence: 99%

Active Auto-Suppression Current Unbalance Technique for Parallel-Connected Silicon Carbide MOSFETs

2022

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Nowadays, medium- and high-power applications make use of silicon carbide (SiC) MOSFETs, and many times their parallelization is necessary. Unfortunately, this requirement causes an inevitable current unbalance between power devices, affecting the performance of power switches. Over the last decade, numerous studies have been conducted, proposing various techniques with the capability of mitigating current unbalance for a number of discrete parallel SiC MOSFETs. However, the realization of most methods requires knowledge of the technical characteristics of power devices, adding extra cost to the system, since screening is a time-consuming and costly process. This necessity reduces the possibilities of such a technique being implemented in power electronics applications, preventing the exploitation of the exceptional features of SiC MOSFETs. In addition, most of these techniques can suppress only the current unbalance, which occurs during turn-on and turn-off transitions. In this paper, an active auto-suppression current unbalance technique is proposed, requiring no device screening. The active method is a closed-loop system capable of sensing and eliminating the entire current unbalance between parallel SiC MOSFETs automatically, actively, and independently of the cause. Simulation results are presented to demonstrate the feasibility and effectiveness of the proposed technique.

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“…The result shows that V th affects the dynamic current distribution, the device with low V th turns-on earlier than the others and turns-off later than the others, and has the largest current during the switching dynamic. In [10], the influence of g fs on the current sharing of paralleled SiC MOS-FETs is analysed. In [29], the study indicates that the difference of R ds impacts the static current sharing.…”

Section: Introductionmentioning

confidence: 99%

Effect of common branch impedance coupling and mutual inductance on current sharing of paralleled SiC MOSFETs with different layouts

Zhao

Ke²,

et al. 2021

IET Power Electronics

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Overcurrent failure caused by imbalanced current distribution is one of the universal failure forms of the SiC MOSFET module. The current sharing of parallel SiC MOSFETs is an important guarantee for the safe and reliable operation of parallel devices even the whole system. The existence of current coupling has a significant influence on the current sharing among paralleled SiC MOSFETs. Here, the mechanism of dynamic and static current imbalance under the different layouts resulting from current coupling generated by common branch impedance coupling and mutual inductance is comprehensively investigated by theoretical analysis and simulation validations. It is concluded that dynamic current imbalance is more serious when the drain confluence point and power source confluence point are on both sides than they are on the one side. While, the influence of the arrangement of two confluence points on the static current distribution is in reverse. Finally, a flexible and adjustable test bench is designed to verify the current sharing performance on the different layouts. The experimental results validate the correctness of the theoretical analysis. Based on these results, some guidelines are provided for the parallel‐connected application of SiC MOSFETs.

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Chips Classification for Suppressing Transient Current Imbalance of Parallel-Connected Silicon Carbide MOSFETs

Cited by 37 publications

References 21 publications

Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices

Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices

Active Auto-Suppression Current Unbalance Technique for Parallel-Connected Silicon Carbide MOSFETs

Effect of common branch impedance coupling and mutual inductance on current sharing of paralleled SiC MOSFETs with different layouts

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