Chip size BGA packaging for high performance memory

Solberg, Vern

doi:10.1109/isaom.2001.916558

Cited by 1 publication

(1 citation statement)

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“…Three-dimensional packaging technology includes stacked dies, stacked packages, and other solutions where the components are mounted in several layers above each other. SIP provides more integration flexibility, faster time to market, and lower product research and development cost than SOC [6].…”

Section: Introductionmentioning

confidence: 99%

Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives

Sharifi

Choi

Mohammadi³

2007

IEEE Trans. Adv. Packag.

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This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 m are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-m CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved.Index Terms-Heterogeneous integration, packaging, systemon-chip (SOC), system-on-package (SIP), wafer-scale integration.

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Section: Introductionmentioning

confidence: 99%