Chip Package Interaction (CPI) risk assessment of 22FDX<sup>®</sup> Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling

Machani, Kashi Vishwanath; Kuechenmeister, Frank; Breuer, D.; Klewer, Christian; Cho, Jae Kyu; Young-Fisher, Kristina

doi:10.1109/ectc32862.2020.00177

Cited by 10 publications

(1 citation statement)

References 2 publications

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“…For traditional integrations, due to the thicker substrate and larger trace width/pitch, axisymmetric FEA models can meet the efficiency and accuracy requirements for DFR. Using a 2D axisymmetric model, Lee et al [ 20 ], Che et al [ 21 ] and Machani et al [ 22 ] simplified the RDLs into homogeneous rectangles and refined the outermost bump, then evaluated the fatigue life of the bump through transient simulation. Using a 3D axisymmetric model, Lee et al [ 23 ] and Che et al [ 24 ] simplified the RDL into homogeneous films and refined the corner solder, thus assessing the reliability of stacked-chip packages.…”

Section: Introductionmentioning

confidence: 99%

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Wu,

Wang,

et al. 2023

Micromachines

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The decreasing-width, increasing-aspect-ratio RDL presents significant challenges to the design for reliability (DFR) of an advanced package. Therefore, this paper proposes an ML-based RDL modeling and simulation method. In the method, RDL was divided into blocks and subdivided into pixels of metal percentage, and the RDL was digitalized as tensors. Then, an ANN-based surrogate model was built and trained using a subset of tensors to predict the equivalent material properties of each block. Lastly, all blocks were transformed into elements for simulations. For validation, line bending simulations were conducted on an RDL, with the reaction force as an accuracy indicator. The results show that neglecting layout impact caused critical errors as the substrate thinned. According to the method, the reaction force error was 2.81% and the layout impact could be accurately considered with 200 × 200 elements. For application, the TCT maximum temperature state simulation was conducted on a CPU chip. The simulation indicated that for an advanced package, the maximum stress was more likely to occur in RDL rather than in bumps; both RDL and bumps were critically impacted by layouts, and RDL stress was also impacted by vias/bumps. The proposed method precisely concerned layout impacts with few resources, presenting an opportunity for efficient improvement.

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Section: Introductionmentioning

confidence: 99%

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Wu,

Wang,

et al. 2023

Micromachines

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Fan-In Wafer/Panel-Level Chip-Scale Packages

Lau

2021

Semiconductor Advanced Packaging

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State-Of-The-Art of Advanced Packaging

Lau¹

2023

Chiplet Design and Heterogeneous Integration Packaging

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Chip Package Interaction (CPI) risk assessment of 22FDX^® Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling

Cited by 10 publications

References 2 publications

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Fan-In Wafer/Panel-Level Chip-Scale Packages

State-Of-The-Art of Advanced Packaging

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Chip Package Interaction (CPI) risk assessment of 22FDX® Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling

Cited by 10 publications

References 2 publications

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

An RDL Modeling and Thermo-Mechanical Simulation Method of 2.5D/3D Advanced Package Considering the Layout Impact Based on Machine Learning

Fan-In Wafer/Panel-Level Chip-Scale Packages

State-Of-The-Art of Advanced Packaging

Contact Info

Product

Resources

About

Chip Package Interaction (CPI) risk assessment of 22FDX^® Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling