Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis

Duo, Xinzhong; Zheng, Lirong; Tenhunen, Hannu

doi:10.1109/epep.2003.1249999

Cited by 9 publications

(7 citation statements)

References 8 publications

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“…The statistics of those parameters (including variation range, distribution function, etc) are also collected and are appended to the initial models of the components. The circuits are designed with these components [9].Statistical responses of the components and the RF SoP modules are studied through Monte Carlo method. If the yield of the circuits obtained from the statistical analysis is not good enough, optimization of the circuits should be implemented in next step.…”

Section: Statistical Modeling and Improvement For Rf Designmentioning

confidence: 99%

Statistical Approach to Design Low Noise Amplifier

Khan¹,

Burney²

2011

IJCEE

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CMOS transistors have been consistently scaled to smaller feature sizes and continue to reduce towards sub-0.1 um lengths. However, as the channel length decreases, so does the gate oxide thickness, dictating a decrease in the supply voltage. Driven by the needs for low power, small size and low cost, CMOS radio frequency integrated circuits (RFIC) design becomes main stream in modern portable wireless communications. The ultimate goal in RFIC design is to having battery-less systems so as to decrease power dissipation. Commonly a Low Noise Amplifier (LNA) is a key component is RF front end receiver which poses a challenge in terms of meeting high gain, low noise figure, good linearity and low power consumption requirement. The primary role of the LNA is to lower the overall noise figure of the entire RF front end, noise optimization is considered as one of the most critical steps in the LNA design procedure. A 0.7V, 1GHz low noise amplifier has been designed and simulated using spectre simulator in a standard TCMC 0.18um CMOS technology. With low power noise optimization techniques, the amplifier provides the gain of 23dB, a noise figure of only 1.1dB, power dissipation of 8.4mw from 0.7v power supply.

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Section: Statistical Modeling and Improvement For Rf Designmentioning

confidence: 99%

Statistical Approach to Design Low Noise Amplifier

Khan¹,

Burney²

2011

IJCEE

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“…A co-design methodology used in the research SSN noise and the effect of decoupling capacitor to the PDN system, through the signal path, the signal transmission distance and PVT(process, voltage and temperature)study, elaborated Chip-Package-PCB co-analysis the feasibility of the method [2]. Another chippackage co-design method to study the mixed-signal circuit to considering the impact of the package's on the overall system performance to improving the accuracy and efficient of the analysis [3] [4]. Use of chip-package-PCB co-analysis method to study the SI and PI problem of high-speed DDR3 system, by modeling the command / address line, and a fly-by topology method to analysis the command / address line of discontinuity and SI problem; meanwhile, modeling of PDN and comprehensive analysis of the data bus SSN [5].…”

Section: Introductionmentioning

confidence: 99%

Signal-power integrity co-simulations of high speed systems via chip-package-PCB co-analysis methodology

Wen

Jing

2013

2013 14th International Conference on Electronic Packaging Technology

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Under the platform of a high-speed package system, a modeling method considering all the signi cant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity(SI/PI). For SI issues, accurate modelings for signal channel are verified by system of high speed line. The following what-if analyses help to identify the package trace's bottlenecks and have great effects on signal transmission. For PI part, the modeling methodologies for power distribution networks of data line are demonstrated and validated with the results of frequency domain simulation. Lastly, with the co-simulations by chippackage-PCB model, the paper was talked about the SI and PI problem using SI-PI co-analysis methodology. The analysis results indicates that the parasitic effects of the high speed package system are the most critical, depicting the importance of improved package design in the next high speed package system.

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“…Due to technical limitation, feature size of conductors are at 100-400um. In the second method, we use the same approach as our in-house developed SoP technology with embedded chip in LCP substrate [12][13][14][15][16]. This is a deposition and lithography based technology in which photo-BCB are coated via pin-off technique for interlayer conductor isolation and vias are etched for interlayer interconnection.…”

Section: B System Integration Issuesmentioning

confidence: 99%

Embedded smart systems for intelligent paper and packaging

Zheng

Shen

Duo

et al.

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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In this paper, we present architecture, circuit implementation and integration issues of an embedded smart system for innovative, long-range interconnected identification/sensor network in warehouse and intelligent goods distribution systems. The network is interconnected via IEEE 802.11 and ultra-wideband (UWB) wireless air interfaces. A self-powered, ultra-low power UWB transceiver with BPSK modulation is designed for transponders and implemented in 0.18um CMOS technology. Low power consumption is achieved by developing innovative circuit and system architectures. Instead of pumping up energy from the Gaussian pluses emitted by the reader, a power converter draws energy from the 802.11 access point and its surrounding electromagnetic waves. Functionality of the transceiver is verified and integration issues for smart labels are investigated on thin foils of liquid crystal polymer.

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Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis

Cited by 9 publications

References 8 publications

Statistical Approach to Design Low Noise Amplifier

Statistical Approach to Design Low Noise Amplifier

Signal-power integrity co-simulations of high speed systems via chip-package-PCB co-analysis methodology

Embedded smart systems for intelligent paper and packaging

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