Chip-Package Co-Design for Optimization of 5.8 GHZ Lna Performance Based on Embedded Inductors

Abstract

This paper presents the design and demonstration of an optimized land grid array (LGA) structure for low noise amplifier (LNA). In order to achieve better circuit performance, the novel chippackage co-design method based on embedded inductors is used. The optimized structure is accurately modeled by ANSYS software. S-parameter is utilized to help in understanding the contributing to the optimized LGA structure. The simulation results for the novel LNA co-design structure show the gain 14.35 dB (> 10 dB), input reflection coefficient −15.63 dB (< −10 dB), output reflection coefficient −24.43 dB (< −10 dB), reverse-isolation −44.7 dB (< −20 dB), and noise figure 2.99 dB (< 4 dB), and indicate that the optimized LGA structure based on embedded inductors is fully capable of supporting 5.8 GHz LNA application. 1. INTRODUCTION With the continuous development of information technology, the demand for low cost and high performance communication systems is increasing. In most RF circuit blocks, low noise amplifiers are usually designed as a single-port circuit for connecting with the band-pass filter or antenna [1, 2]. In order to achieve an efficient input power matching, many on-chip inductors are used in LNA design. These on-chip inductors, implemented in Complementary Metal Oxide Semiconductor transistor (CMOS) technology, not only consume high silicon area, but also have poor electrical performances [3], such as low quality factors. On the other hand, as the operating frequency or bandwidth increases for high data rate, the LNAs become more susceptible to package effects. Those package parasitic effects will cause significant degradation in gain and impedance of LNAs [4]. In previous works, the conventional ceramic quad flat no-lead (QFN) package is usually used for LNA design to satisfy highperformance [5, 6]. The low-pass filter models are used for wire bond packaged LNAs to reveal the package input/output interconnect behave and like an impedance transformer in altering the matching network for optimization design. In this paper, a chip-package co-design of 5.8 GHz cascade common-source LNA based on embedded inductors is presented. In view of electrical performance design, the matching networks on the package substrate by using embedded inductor are constructed. Designing embedded inductor elements can reduce the number of passive elements and achieve special matching values. In Section 2, a special cascade common-source LNA chip with an on-chip matching network and its performance is discussed in detail. Then, the embedded inductor on the LGA substrate is built and analyzed in Section 3. By taking advantage of the packaging parasitic of bond wire, the LNA co-design architecture is established and optimized in Sections 4-5. Finally, a brief conclusion is given in Section 6.