CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

Prabhu, Kartik; Gural, Albert; Khan, Zainab F.; Radway, Robert M.; Giordano, Massimo; Koul, Kalhan; Doshi, Rohan; Kustin, John W.; Liu, Timothy; Lopes, Gregorio B.; Turbiner, Victor; Khwa, Win-San; Chih, Yu-Der; Chang, Meng‐Fan; Lallement, Guénolé; Murmann, Boris; Mitra, Subhasish; Raina, Priyanka

doi:10.1109/jssc.2022.3140753

Cited by 21 publications

(2 citation statements)

References 41 publications

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“…The ASIC-based processing system consists of a hardware accelerator and off-chip DRAM and storage 54 . The recently reported CHIMERA accelerator (40 nm CMOS technology) 55 with 0.92 TOPS on peak performance and 2.2 TOPS/W on energy efficiency is adopted for the evaluation. DDR4 DRAM with 8 memory controllers and 64-bit channel per controller is utilized as external memory, which reported 45 pJ/bit on read/write energy and 65 ns/60 ns on read/write latency 56 .…”

Section: Methodsmentioning

confidence: 99%

Memristor-based storage system with convolutional autoencoder-based image compression network

Feng,

Zhang,

Zhou

et al. 2024

Nat Commun

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The exponential growth of various complex images is putting tremendous pressure on storage systems. Here, we propose a memristor-based storage system with an integrated near-storage in-memory computing-based convolutional autoencoder compression network to boost the energy efficiency and speed of the image compression/retrieval and improve the storage density. We adopt the 4-bit memristor arrays to experimentally demonstrate the functions of the system. We propose a step-by-step quantization aware training scheme and an equivalent transformation for transpose convolution to improve the system performance. The system exhibits a high (>33 dB) peak signal-to-noise ratio in the compression and decompression of the ImageNet and Kodak24 datasets. Benchmark comparison results show that the 4-bit memristor-based storage system could reduce the latency and energy consumption by over 20×/5.6× and 180×/91×, respectively, compared with the server-grade central processing unit-based/the graphics processing unit-based processing system, and improve the storage density by more than 3 times.

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Section: Methodsmentioning

confidence: 99%

Memristor-based storage system with convolutional autoencoder-based image compression network

Feng,

Zhang,

Zhou

et al. 2024

Nat Commun

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“…Conventional computations are limited in terms of energy efficiency and computing latency because of the frequent movement of neural network parameters and intermediate computing data between processing cores and memory, a problem referred to as the memory wall ( 1 – 3 ). Compute-in-memory (CIM), which refers to a memory block with built-in computing functions, can largely overcome this bottleneck by performing multiple dot-product operations within the memory cell array.…”

mentioning

confidence: 99%

Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing

Wen,

Hung,

Huang

et al. 2024

Science

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Artificial intelligence (AI) edge devices prefer employing high-capacity nonvolatile compute-in-memory (CIM) to achieve high energy efficiency and rapid wakeup-to-response with sufficient accuracy. Most previous works are based on either memristor-based CIMs, which suffer from accuracy loss and do not support training as a result of limited endurance, or digital static random-access memory (SRAM)–based CIMs, which suffer from large area requirements and volatile storage. We report an AI edge processor that uses a memristor-SRAM CIM-fusion scheme to simultaneously exploit the high accuracy of the digital SRAM CIM and the high energy-efficiency and storage density of the resistive random-access memory memristor CIM. This also enables adaptive local training to accommodate personalized characterization and user environment. The fusion processor achieved high CIM capacity, short wakeup-to-response latency (392 microseconds), high peak energy efficiency (77.64 teraoperations per second per watt), and robust accuracy (<0.5% accuracy loss). This work demonstrates that memristor technology has moved beyond in-lab development stages and now has manufacturability for AI edge processors.

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DIANA: DIgital and ANAlog Heterogeneous Multi-core System-on-Chip

Jain,

Verhelst

2023

Towards Heterogeneous Multi-Core Systems-on-Chip for Edge Machine Learning

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CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference

Cited by 21 publications

References 41 publications

Memristor-based storage system with convolutional autoencoder-based image compression network

Memristor-based storage system with convolutional autoencoder-based image compression network

Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing

DIANA: DIgital and ANAlog Heterogeneous Multi-core System-on-Chip

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