Chemical reaction concerns of gate metal with gate dielectric in Ta gate MOS devices: an effect of self-sealing barrier configuration interposed between Ta and SiO/sub 2/

Ushiki, T.; Kawai, K.; Ohshima, Ichiro; Ohmi, Tadahiro

doi:10.1109/16.877184

Cited by 17 publications

(6 citation statements)

References 28 publications

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“…Since the reaction product is amorphous, it is experimentally the very difficult to distinguish between the different phases that may be present. The instability of this interface is consistent with observations [13] and predictions [10] by others.…”

Section: Resultssupporting

confidence: 92%

See 1 more Smart Citation

Stability of Ru‐ and Ta‐based metal gate electrodes in contact with dielectrics for Si‐CMOS

Chen

Misra

Haggerty

et al. 2004

Physica Status Solidi (b)

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The Ru–Ta–Si–O, Ta–Si–N–O, and Ru–Ta–Zr–O phase diagrams are important for predicting reactions at interfaces between SiO2 and ZrO2 gate dielectrics and novel Ru and Ta‐based metal gate electrodes. Simplified quaternary phase diagrams of the Ru–Ta–Si–O, Ta–Si–N–O, and Ru–Ta–Zr–O systems at 900 °C were constructed from known and estimated Gibbs free energy data, respectively. Ru is predicted to be stable in contact with ZrO2 and SiO2, whereas Ta is not stable in contact with SiO2 at temperatures around 900 °C. Stoichiometric RuTa and TaN compounds were estimated to be stable in contact with both dielectrics at 900 °C. Experimental observations of gate electrode/dielectric interfaces are discussed. They are consistent with the thermodynamic predictions within the limitations of these phase diagrams. Metastable phases, often found in TaNx films, and diffusion of species from the vapor (e.g., oxygen), in particular along grain boundaries in columnar gate electrodes, may lead to reactions not predicted by the equilibrium phase diagrams. (© 2004 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Resultssupporting

confidence: 92%

“…The phase diagram for the quaternary Ru-Ta-Si-O system is necessary to evaluate the stability of RuTa compounds on SiO 2 . The four isothermal (900 °C) ternary systems, Ta [11,13,18,19]. The calculated Ta-Si-O phase diagram at 900 °C is shown in Fig.…”

Section: The Ru-ta-si-o Systemmentioning

confidence: 99%

Stability of Ru‐ and Ta‐based metal gate electrodes in contact with dielectrics for Si‐CMOS

Chen

Misra

Haggerty

et al. 2004

Physica Status Solidi (b)

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“…However, during the actual sample deposition and integration procedures, metal gate inevitably reacts with gate dielectric substrate. This reaction between them can induce metal contamination in thin gate dielectric 3 – 5 and fermi level pinning 6 which makes the EWF of gate electrode to deviate from the desired value. As a result, reliability and performance of device has been degraded.…”

Section: Introductionmentioning

confidence: 99%

Effects of graphene intercalation on dielectric reliability of HfO2 and modulation of effective work function for Ni/Gr/c-HfO2 interfaces: first-principles study

Zhong

Yang

Zhang

et al. 2018

Sci Rep

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We have investigated the effects of graphene intercalation on dielectric reliability of HfO2 for Ni/Gr/HfO2 interfaces, and the effects of graphene intercalation and interfacial atom vacancy on the effective work function (EWF) of Ni/Gr/HfO2 interfaces using first-principle calculation based on density functional theory. The calculated results indicate that graphene intercalation can improve dielectric reliability of HfO2 dielectric even for the interfaces having interfacial oxygen vacancy or a small amount carbon vacancy. Moreover, the calculated results indicate that, inserting graphene into Ni/HfO2 interface induces the EWF’s to decline, and controlling interfacial oxygen or carbon vacancy can effectively tune the EWF of Ni/Gr/HfO2 interface. Our work strongly suggests that the use of graphene synthesized into Ni/HfO2 interface is a very effective way to improve the interface quality, and controlling interfacial oxygen or carbon vacancy is also an attractive and promising way for modulating the EWF of Ni/Gr/HfO2 interfaces.

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“…Previously, several attempts were made to prevent plasma damage caused by sputtering deposition process. Ushiki et al 6,7 investigated the effects of ion species in sputtering deposition on the gate oxide reliability, and showed that Xe plasma sputtering deposition suppresses plasma-induced gate oxide damage by reducing the physical bombardment energy of Xe ion as compared to Ar plasma deposition. Takeuchi et al demonstrated that the introduction of plasma charge trap to dc-magnetron sputtering system effectively suppresses high-energy particle bombardment to gate dielectric, leading to the improvement in the gate oxide integrity of Mo-gated p-type metal-oxide-semiconductor field-effect transistors ͑PMOSFETs͒ and retention characteristics of Mo-gated nonvolatile memory device.…”

mentioning

confidence: 99%

Er and Pt Gate Electrodes Formed on SiO[sub 2] Gate Dielectrics

Choi

Jung

Kim

et al. 2008

Electrochem. Solid-State Lett.

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We investigated the electrical and structural properties of W/Er/SiO 2 and Pt/SiO 2 gate stacks. W/Er/SiO 2 gate stacks exhibited increased capacitance after rapid thermal annealing ͑RTA͒ process while the capacitance of Pt/SiO 2 gate stacks remained unchangeable regardless of RTA process. Because of the physical plasma damage that occurred during the sputtering deposition process, Pt penetration led to a decrease in the SiO 2 film thickness of Pt/SiO 2 gate stacks. This resulted in the reduction of the equivalent oxide thickness compared to the poly-Si/SiO 2 gate stack. A relatively small flatband voltage shift of W/Er/SiO 2 gate stacks was attributed to the reduction of effective oxide charge caused by interfacial reaction between Er and SiO 2 films.With continuous scaling down of complementary metal oxide semiconductor ͑CMOS͒ to the 45 nm technology node and beyond, a metal gate is expected to replace a conventional polycrystalline silicon ͑poly-Si͒ electrode for realizing a high device performance. The metal gate has superior advantages over the poly-Si gate, such as very low gate resistance, no dopant penetration to channel, and good process compatibility with high-k gate dielectric. 1-4 In addition, it does not suffer from increasing effective oxide thickness ͑EOT͒ caused by poly-depletion effect. 5 Generally, the sputtering deposition method has been widely used for forming metal gate electrodes due to its low cost of operation, low process temperature, and precise controllability of various metal thin layers. However, during sputtering deposition process, the gate dielectric is directly exposed to plasma and intensively irradiated by energetic particles such as ions, electrons, and photon. Such an irradiation creates plasma damage, which degrades the reliability of gate dielectric. Previously, several attempts were made to prevent plasma damage caused by sputtering deposition process. Ushiki et al. 6,7 investigated the effects of ion species in sputtering deposition on the gate oxide reliability, and showed that Xe plasma sputtering deposition suppresses plasma-induced gate oxide damage by reducing the physical bombardment energy of Xe ion as compared to Ar plasma deposition. Takeuchi et al. demonstrated that the introduction of plasma charge trap to dc-magnetron sputtering system effectively suppresses high-energy particle bombardment to gate dielectric, leading to the improvement in the gate oxide integrity of Mo-gated p-type metal-oxide-semiconductor field-effect transistors ͑PMOSFETs͒ and retention characteristics of Mo-gated nonvolatile memory device. 8 It was also reported that the atomic-layer-deposited buffer layer on which metal gate was sputter deposited was effective in minimizing plasma damage to underlying ultrathin dielectric film. 9 In this work, a comparative study on electrical and structural properties between W/Er/SiO 2 and Pt/SiO 2 gate stacks was performed. It is shown that the interfacial reaction between Er and SiO 2 films of W/Er/SiO 2 gate stacks could be responsible for the reduc...

show abstract

Chemical reaction concerns of gate metal with gate dielectric in Ta gate MOS devices: an effect of self-sealing barrier configuration interposed between Ta and SiO/sub 2/

Cited by 17 publications

References 28 publications

Stability of Ru‐ and Ta‐based metal gate electrodes in contact with dielectrics for Si‐CMOS

Stability of Ru‐ and Ta‐based metal gate electrodes in contact with dielectrics for Si‐CMOS

Effects of graphene intercalation on dielectric reliability of HfO2 and modulation of effective work function for Ni/Gr/c-HfO2 interfaces: first-principles study

Er and Pt Gate Electrodes Formed on SiO[sub 2] Gate Dielectrics

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