Chemical Nature of Silicon Nitride‐Indium Phosphide Interface and Rapid Thermal Annealing for InP MISFETs

Abstract

Rapid thermal annealing (RTA) of the ion implanted indium phosphide (InP) compound semiconductors in pure nitrogen or hydrogen was investigated for the fabrication of metal-insulator-semiconductor field-effect transistors (MISFETs). InP was encapsulated during RTA by 500A silicon nitride films made using PECVD at 300~ and 500 mtorr with a 13.56 MHz RF power density of 50 mW/cm 2. A sequence of high-resolution x-ray photoelectron spectra were obtained at four depths through the silicon nitride-InP interfacial region for the In 3d5/2, P 2p, N ls, Si 2p, and O ls peaks to determine the chemical nature of the interface after encapsulated RTA. There was a component of the In 3d5/2 peak consistent with In(OH)3, InO-(OH), or InO2 which increased after RTA. No phosphate was observed in the P 2p peak. A significant decrease of the N-H or N-N component of the N ls peak occurred after RTA. Secondary ion mass spectrometry atomic concentration profiles of InP implanted with silicon at 150 keV to a dose of 4 • 1013 cm -2 showed peak atomic concentrations of 2 x 10 TM cm -3 at 0.2 ~m for RTA of 15, 30, or 60s at 700~ in pure N2 or H2. The atomic concentration profiles showed no diffusion of the implanted silicon in the InP during RTA. A pure H2 RTA at 700~ for 30s followed by a furnace anneal at 400~ for 2h in forming gas of the phosphorus oxide/silicon dioxide gate insulator was determined to be the optimum thermal process for the fabrication of InP MISFETs. The MISFETs had threshold voltages of + 1V, transconductance of 27 mS/mm, peak channel mobility of 1200 cm 2 V -1 s -1, and drain current drift of only 7%.

Silicon Dioxide with a Silicon Interfacial Layer as an Insulating Gate For Highly Stable Indium Phosphide Metal‐Insulator‐Semiconductor Field Effect Transistors

“…The 30 min CF4 plasma cleaning was necessary to remove the film deposits on the chamber walls from previous deposition runs. Our previous experiments (17,18) have indicated that 30 min were long enough for the removal of the films from prior runs. Then the substrates were loaded into the chamber immediately after the initial clean to minimize any native oxide growth.…”

“…An argon ion beam was used for surface cleaning which was operated at 2 keV. The details of the XPS technique as applied to insulator/InP interfaces have recently been reported (17,18).…”

“…2c. The details of the RTA system have been described by Biedenbender et al (18). Rapid thermal annealing of encapsulated ion implantation is desirable over furnace annealing in order to reduce dopant diffusion, improve electrical activation, and reduce InP surface damage due to reduced time at high temperatures.…”

Redistribution of Impurities during Thermal Oxidation of Polycrystalline Silicon

“…Consider the oxidation of gate d~ is also expressed in general as d~ = d(LhNpol:0 [19] Combining Eq. [18] and [19] and assuming dh = dL, Npoly is solved as Npol, = No ho \Ifo/ [20] where Lo is the initial gate length. Thus, the two-dimensional effect is expressed by the factor…”