Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers

Abstract

Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced.

Identifying nano-Schottky diode currents in silicon diodes with 2D interfacial layers

“…As opposed to the ideal low-electron-current case, if the electron current became decades higher than the hole current, the level and ideality of ∆IE were affected [10,11]. An example with Schottky diode emitter and collector is shown in Fig.…”

“…The conclusions are based on statistical data, measurement of arrays of diodes with varying geometry, and temperaturedependent characteristics. In addition, a special bipolar-type measurement using the 2-diode method [10,11] is described and evaluated as an aid in identifying nano-Schottky behavior. Specific 2-diode test structures that can be used as a means to confirm the localized nature of a nano-Schottky are also discussed.…”