Charon: Load-Aware Load-Balancing in P4

Rizzi, Carmine; Yao, Zhiyuan; Desmouceaux, Yoann; Townsley, Mark; Clausen, Thomas

doi:10.23919/cnsm52442.2021.9615535

Cited by 5 publications

(5 citation statements)

References 18 publications

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“…They use hash to select DIPs at switches, and employ SLBs to mitigate (cannot avoid) PCC violations. Recently there has existed a number of proposals where load balancing logic is offloaded into programmable hardwares [7,[9][10][11][12][13][14], the primary impetus behind that is offering programmability and significant performance. Beamer [14] presents stable hashing for DIP selection, and exploits daisy chaining to ensure PCC, but still may incur PCC violations under frequent DIP pool updates.…”

Section: Related Workmentioning

confidence: 99%

“…SHELL [9] employs IPv6 Segment Routing combined with power-of-two-choice (Pow2) to distribute connections among servers based on CPU load. Charon [12] combines Pow2 with load states of servers based on the remaining number of active flows. To avoid breaking PCC, they encapsulate related state in packet header.…”

Section: Related Workmentioning

confidence: 99%

“…Load-agnostic LBs make load balancing decisions without considering load status of servers, mostly relying on consistent hashing [2] or hash to dispatch connections at random [1,[3][4][5][6][7][8], which thus cannot achieve load balancing fairness. Moreover, load-aware LBs take into account load status of servers but the metrics considered are onefold, most of which distribute connections merely based on CPU load, response time, or the number of active connections of servers [9][10][11][12]. This cannot reflect a ctual s tates o f servers and still may lead to unfair load distribution among servers.…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, PCC requirement should also be satisfied during making load balancing decisions and has been the focus of many prior works [1,[3][4][5][6][7][8][9][10][11][12][13][14][15][16]. In both existing load-agnostic and load-aware LBs, simple load balancing mechanisms are employed so that mitigating PCC violations.…”

Section: Introductionmentioning

confidence: 99%

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Libra: A Stateful Layer-4 Load Balancer with Fair Load Distribution

Guo

Zhu

Zhang

et al. 2022

2022 IEEE International Performance, Computing, and Communications Conference (IPCCC)

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thing, LBs cannot achieve load balancing fairness by virtue of simple load balancing mechanisms as stated previously. For another, many LBs cannot avoid PCC violations upon frequent DIP pool updates [4-6, 9, 14]. Hence, existing LBs cannot achieve load balancing fairness and PCC at the same time, both of which substantially increase tail latency of services.In response, this paper presents Libra, a stateful LB implemented in a P4 switch, in which a more sophisticated load balancing mechanism (i.e., Weighted M-Least-Connection First (WMLCF)) considering actual states of servers is designed to achieve load balancing fairness and meanwhile PCC is guaranteed in a memory-efficient way in the data plane. Nevertheless, this poses three key challenges: i) it is challenging to implement WMLCF mechanism in the data plane that only supports simple arithmetic computations operating nonfloating point values; ii) implementing the mechanism without violating PCC as the complicated mechanism could incur more PCC violations; and iii) achieving load balancing fairness and PCC without sacrificing performance. Libra copes with these challenges via the following designs: i) we implement WMLCF by means of the collaboration of the data plane and the control plane; ii) we introduce Bloom Filter [17] with small size to avoid PCC violations incurred by WMLCF and DIP pool updates; and iii) WMLCF is implemented in the control plane while Libra makes load balancing decisions in the data plane, which ensures the line-rate packet processing.To summarize, Libra makes four major contributions as follows:• We introduce Libra, a stateful LB that primarily achieves load balancing fairness and PCC. We present the architecture and detailed design of Libra. • We propose and implement a novel load balancing mechanism (i.e., WMLCF) that can fairly spread the load among servers. Libra makes load balancing decisions in the light of WMLCF mechanism. • We ensure PCC even under the more PCC violations induced by the usage of more complicated load balancing mechanism and DIP pool updates, which incurs marginal memory overhead. • We implement Libra on a P4 software switch, and conduct extensive evaluations to demonstrate the capability of Libra in terms of achieving load balancing fairness and PCC. The evaluation shows that, compared with existing LBs, Libra can achieve load balancing fairness above 95% even under heavy load and fully ensuring PCC under various scenes.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Libra: A Stateful Layer-4 Load Balancer with Fair Load Distribution

Guo

Zhu

Zhang

et al. 2022

2022 IEEE International Performance, Computing, and Communications Conference (IPCCC)

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“…Among them, some smart-NICs and the Barefoot Tofino programmable switch [58]. Since, a lot of research papers have been using P4 programmable devices to offload some tasks to the network [126,110,68,69].…”

Section: Programmable Networkmentioning

confidence: 99%

Towards new memory paradigms : integrating non-volatile main memory and remote direct memory access in modern systems

Dulong

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Modern computers are built around two main parts: their Central Processing Unit (CPU), and their volatile main memory, or Random Access Memory (RAM). The basis of this architecture takes its roots in the 1970's first computers. Since, this principle has been constantly upgraded to provide more functionnality and performance.In this thesis, we study two memory paradigms that drastically change the way we can interact with memory in modern systems: non-volatile memory and remote memory access. We implement software tools that leverage them in order to make them compatible and exploit their performance with concrete applications. We also analyze the impact of the technologies underlying these new memory medium, and the perspectives of their evolution in the coming years.For non-volatile memory, as the main memory performance is key to unlock the full potential of a CPU, this feature has historically been abandoned on the race for performance. Even if the first computers were designed with non-volatile forms of memory, computer architects started to use volatile RAM for its incomparable performance compared to durable storage, and never questioned this decision for years. However, in 2019 Intel released a new component called Optane DC Persistent Memory (DCPMM), a device that made possible the use of Non-Volatile Main Memory (NVMM). That product, by its capabilities, provides a new way of thinking about data persistence. Yet, it also challenges the hardware architecture used in our current machines and the way we program them.With this new form of memory we implemented NVCACHE, a cache designed for non-volatile memory that helps boosting the interactions with slower persistent storage medias, such as Solid State Drive (SSD). We find NVCACHE to be quite performant for workloads that require a high granularity of persistence guarantees, while being as easy to use as the traditional POSIX interface. Compared to file systems designed for NVMM, NVCACHE can reach similar or higher throughput when the non-volatile memory is used. In addition, NVCACHE allows the code to exploit NVMM performance while not being limited by the amount of NVMM installed in the machine.Another major change of in the computer landscape has been the popularity of distributed systems. As individual machines tend to reach performance limitations, iii

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