In this work, we demonstrate that conductive atomic force microscopy ͑C-AFM͒ is a very powerful tool to investigate, at the nanoscale, metal-oxide-semiconductor structures with silicon nanocrystals ͑Si-nc͒ embedded in the gate oxide as memory devices. The high lateral resolution of this technique allows us to study extremely small areas ͑ϳ300 nm 2 ͒ and, therefore, the electrical properties of a reduced number of Si-nc. C-AFM experiments have demonstrated that Si-nc enhance the gate oxide electrical conduction due to trap-assisted tunneling. On the other hand, Si-nc can act as trapping centers. The amount of charge stored in Si-nc has been estimated through the change induced in the barrier height measured from the I-V characteristics. The results show that only ϳ20% of the Si-nc are charged, demonstrating that the electrical behavior at the nanoscale is consistent with the macroscopic characterization. Memory devices based on metal-oxide-semiconductor ͑MOS͒ structures with Si nanocrystals ͑Si-nc͒ embedded in the gate oxide 1-5 show many advantages compared to the current floating gate technologies. In particular, they offer fast writing speeds at smaller injection voltages, extremely small degradation, smaller lateral leakage currents, and, therefore, longer retention times. These developments in nanoscale silicon electronics, however, require tools to locally characterize the electrical properties of the Si-nc. In this direction, conductive atomic force microscopy 6-8 ͑C-AFM͒ has been recently used to estimate from topographical images the amount of charge stored in Si-nc deposited on different substrates. 9,10 However, few works have been devoted to investigate the electrical properties of MOS-based memory devices with embedded Si-nc at the nanoscale. In this work, a C-AFM has been used to study the conduction mechanisms of SiO 2 gate oxides with Si-nc as storage nodes. The amount of charge stored in few Si-nc has also been estimated from electrical measurements.MOS structures with a SiO 2 thickness, t ox , of 23 nm ͓ob-tained from transmission electron microscopy ͑TEM͒ images͔ thermally grown on a p-type Si substrate and with a polysilicon gate have been analyzed. In some of them, the gate oxide was implanted with 15-keV Si + ions with a dose of 2 ϫ 10 16 cm −2 . 2 The peak concentration was estimated by simulation to be of about 10 at. % at a depth of ϳ22 nm with a width at half maximum of the ion implantation distribution within the oxide of ϳ9 nm. The rest were used as a measurement reference. After removing the polysilicon gate, 8 when working on bare oxides, the conductive tip of the C-AFM plays the role of the gate electrode. Therefore, MOS structures of only ϳ300 nm 2 can be analyzed. 8 The gate oxides ͑with and without Si-nc͒ were electrically characterized by measuring current-voltage ͑I-V͒ characteristics, obtained when a ramped voltage test ͑RVS͒, which consists of a forward followed by a backward voltage ramp, is applied at a fixed location of the oxide.To begin with, the electrical conduction of...