Charging effects in silicon nanocrystals within SiO2 layers, fabricated by chemical vapor deposition, oxidation, and annealing

Abstract

Metal–insulator–semiconductor structures with a layer of silicon nanocrystals embedded within the SiO2 layer at a tunneling distance from a p-type silicon substrate and fabricated using chemical vapor deposition, oxidation, and annealing, exhibited charge trapping, determined from the capacitance–voltage (C–V) characteristics, which abruptly increased at fields above 2.5 MV/cm. Electrons or holes are trapped when biasing the structure into inversion or accumulation, respectively, and retention of trapped charge is demonstrated. The I–V characteristics exhibit an N-shaped form, indicating screening effects due to charging; an initial current spike, attributed to transient charging of nanocrystals, occurs at the same voltage causing abrupt C–V shift increase, with Fowler–Nordheim current rising at higher voltages. These structures are promising for memory device applications.

Electrical and electroluminescent characterization of nanometric multilayers of SiOX/SiOY obtained by LPCVD including non-normal emission

“…This behavior has been attributed to the charge trapping mechanism at the nc-Si/SiO 2 interface. 14 Meantime, Crupi et al have reported that this behavior is attributed to leakage current because a thin layer of dielectric is used, propitiating electrons or holes to tunnel from the dielectric layer to the contact or substrate. 15 Another report mentions that an inadequate maximum capacitance is measured because of a poor ohmic contact between gate and dielectric; thus, a thin layer of air is located between them, producing a series capacitance respect to the oxide capacitance.…”

Silicon Nanocrystal Flash Memory

“…It is also worthwhile to figure out that hole trapping in the nc-Si dots is absent due to the higher energy barrier for holes at the valence band of Si/SiO 2 system, but possible at a relative large erasing voltage. Both electron and hole trapping in the nc-Si dots were identified by Nassiopoulou [65]. The hole trapping in the nc-Si dots may lead to negative shifts in C-V or current-voltage (I-V) curves like a positive shift by the electron accommodation.…”

C60 Nanostructures for Applications in Information Technology

“…Therefore, C 60 is usually deposited onto a thermally oxidized tunneling oxide O. Senftleben et al/C 60 Nanostructures for Applications and is then covered by deposition of a control oxide on top. This can either be done by PECVD [22,23] , by CVD growth of amorphous silicon and subsequent thermal oxidation [24,25] , by co-evaporation of silicon in an oxygen ambient [26,27] or by a low pressure chemical vapor deoposition (LPCVD) process using, e.g., tetraetoxysilane (TEOS) as a precursor [28,29] , which requires a high thermal budget of around 700 8C. The stability and the desorption behavior of C 60 in oxygen atmosphere under elevated temperatures is, therefore, of high interest.…”