Charge Trapping at the Dielectric of Organic Transistors Visualized in Real Time and Space

Abstract

Recently the commercialization of the first reflective organic displays employing organic field-effect transistors (OFETs) used for on-off switching of pixels was announced. These new electrophoretic displays are bistable and have low power consumption. Future, emissive, organic light-emitting displays (OLEDs), however, will operate at high powers and then reliability and excellent long-term stability OFETs will be crucial for stable operation. Unfortunately, OFETs commonly suffer significantly from gate-bias stress under ambient conditions that, over time, causes a detrimental shift in the voltage that the device requires to switch. This threshold-voltage shift limits the exploitation of the full potential of organic semiconductors and OFETs in low-cost, large-area, flexible applications. As an example, using current technologies OLEDs would require up to four driving OFETs per pixel to compensate for the threshold voltage shift in the transistors.[1] This demonstrates the urgency for a proper understanding of the stressing mechanism. In practice, OFETs are hybrid material devices that consist of metallic contacts, an inorganic gate dielectric, and an organic semiconductor. Silicon dioxide is commonly used as the gate dielectric. Although the top layer of SiO 2 is known to contain trap sites for charge carriers, [2] it is presently not clear if these traps are related to the bias-stress effect, and, if so, how this is affected by environmental conditions such as humidity. [3][4][5][6][7][8][9] In this Communication, the dynamics of trapping and detrapping of charges on bare SiO 2 are visualized in real time and space using scanning Kelvin probe microscopy (SKPM) and compared to the bias-stressing dynamics of an organic field-effect transistor using a SiO 2 dielectric. The results clearly show that the generally observed gate-bias stress effect in OFETs is due to water-related charge trapping at the SiO 2 surface, rather than to trapping in the organic semiconductor itself. This insight rationalizes previous results [3][4][5][6][7][8][9] and gives credence to the argument that the surface of the inorganic gate dielectric determines the reliability of organic transistors. We further explain why passivating the SiO 2 surface or decreasing the ambient humidity results in a significant reduction in the bias stress. For our studies, we used a polytriarylamine (PTAA) (Merck, UK) that yields reproducible transistors with a hole mobility of 10 -3 -10 -2 cm 2 V -1 s -1 .[10] The chemical structure of PTAA together with a schematic picture of the cross-section of a transistor is depicted in the inset of Figure 1a. Transistors were fabricated using heavily doped p-type silicon wafers as the common gate electrode with a 200 nm thermally oxidized SiO 2 layer as the gate dielectric. Gold source and drain electrodes were defined by photolithography with a channel width and length of 2500 and 10 lm, respectively. Before depositing gold, a 10 nm titanium adhesion layer was evaporated. The substrates were exposed to a UV-ozone tre...

Proton migration mechanism for operational instabilities in organic field-effect transistors

“…The dynamics of this evolution was found to be determined by the amount of water on the SiO 2 , which could be regulated by treatment with HMDS. 13 The time evolution of the potential profile on this structure shows that charges can move around reversibly on the SiO 2 surface even in absence of a semiconductor. Surprisingly, the time evolution was found to occur on equal time scales for both positive and negative polarity of the drain bias.…”

“…Furthermore, pretreatment of the SiO 2 with hydrophobic HMDS or octadecyltrichlorosilane is is known to decelerate the effect. 9,13 Use of a hydrophobic organic gate dielectric practically eliminates the effect 21 while coverage of the SiO 2 with a layer that is impenetrable to water does the same. 10 These observations indicate that the threshold-voltage shift in organic transistors is related to residual water.…”

“…13 With application of a drain bias ͑and a grounded source and gate͒ a time evolution of the potential profile at the SiO 2 surface was measured. The dynamics of this evolution was found to be determined by the amount of water on the SiO 2 , which could be regulated by treatment with HMDS.…”

“…[5][6][7][8][9][10][11][12][13][14] SiO 2 is chosen to prevent effects of ionic movements, which are known to occur in organic gate dielectrics. 15 Nevertheless, transistors with SiO 2 as gate dielectric suffer from the bias-stress effect.…”

“…Several mechanisms have been suggested as an explanation, such as ͑i͒ trapping of mobile carriers in the bulk of the semiconductor, 17 ͑ii͒ trapping in disordered areas of the semiconductor, 7 ͑iii͒ trapping in regions in between crystalline grains of the semiconductor, 18 ͑iv͒ trapping in states at the semiconductor/dielectric interface, 8 and ͑v͒ pairing of mobile carriers to bipolarons in the semiconductor. 5,19 Two other important observations are that the effect is influenced by humidity 13,20,21 and that the effect is thermally activated, with an activation energy of about 0.6 eV, apparently independent of the organic semiconductor used. 11 Recently, we proposed a mechanism for the bias-stress effect in p-type field-effect transistors with SiO 2 gate dielectric that is based on production of protons from holes and water in the accumulation layer of the semiconductor and the subsequent migration of these protons into the gate dielectric.…”