Charge Trapping Analysis of High Speed Diamond FETs

Abstract

Charge carrier trapping in diamond surface conduction field effect transistors (FETs) has been analyzed. For these devices two methods were used to obtain a negative electron affinity diamond surface; either plasma hydrogenation or annealing in an H2 environment. In both cases the Al2O3 gate dielectric can trap both electrons and holes in deep energy levels with emission timescales of seconds, while the diamond -Al2O3 interface traps exhibit much shorter time scales in the microsecond range. Capacitance-Voltage (CV) analysis indicates that these interface traps exhibit acceptor-like characteristics. Correlation with CV based free hole density measurements indicates that the conductance based interface trap analysis provides a method to quantify surface characteristics that lead to surface conduction in hydrogenated diamond where atmospheric adsorbates provide the acceptor states for transfer doping of the surface.

Two-Dimensional Diamond—Diamane: Current State and Further Prospects

“…It is predicted that the superconducting transition temperature of B-doped diamane and diamond is comparable . One distinct property of diamond is the upward shift of the bands caused by the H-passivation polarity, which enables possible modulation or transfer doping by acceptors at the exterior , preserving high carrier mobility. − This must also be true for the diamane, offering a very attractive field effect transistor channel and at sufficient doping level even a plasmonic device …”

Structural and electronic properties of 2D (graphene, hBN)/H-terminated diamond (100) heterostructures

“…23 Hence, it is widely used in diamond-based RF devices. [24][25][26][27][28][29] Despite these advantages, which makes (100) the most technologically important diamond surface, the lattice mismatch in the hexagonal 2D layer on the diamond complicates the computational studies. As a result, recent computational studies on 2D/diamond heterostructures have utilized the (111) diamond facet to mitigate the interfacial strain.…”

Microwave diamond devices technology: Field‐effect transistors and modeling

“…62 HD MOSFET with the 2DHG surface channel is greatly influenced by the interface traps in the Al 2 O 3 /C H diamond structure. Pulse IV characterizations have been conducted to analyze the gate-lag and drain-lag effects in diamond transistors, 44,63 and the capacitance-voltage (C-V) measurement was utilized to extract the detailed trap levels and densities. 63,64 The Al 2 O 3 /C H diamond interface exhibits acceptorlike interface traps with much shorter time scales in the microsecond range.…”

“…Pulse IV characterizations have been conducted to analyze the gate-lag and drain-lag effects in diamond transistors, 44,63 and the capacitance-voltage (C-V) measurement was utilized to extract the detailed trap levels and densities. 63,64 The Al 2 O 3 /C H diamond interface exhibits acceptorlike interface traps with much shorter time scales in the microsecond range. However, the typical test frequency of the C-V measurement ranges from 1 kHz to 1 MHz, which corresponds to the pulse width varying from 1 millisecond to 1 microsecond.…”