Charge Storage Model for Variable Threshold Fet Memory Element

Sewell, F. A.; Wegener, H. A. R.; Lewis, E.T.

doi:10.1063/1.1652705

Cited by 61 publications

(15 citation statements)

References 5 publications

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“…As many research groups pointed out, charges should be mainly stored in the interface [14,15] and the surface or bulk of Si 3 N 4 layer [9]. If the thickness of SiO 2 layer does not influence the charge storage capability of double layer electrets, it is reasonably induced that the mean charge den- sity and depth are the same for all samples with different SiO 2 thicknesses.…”

Section: Effect Of Different Sio 2 Thicknessesmentioning

confidence: 99%

Study on PECVD SiO2/Si3N4 double-layer electrets with different thicknesses

Zou

Zhang

2011

Sci. China Technol. Sci.

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In this paper, performance of PECVD SiO 2 /Si 3 N 4 double layers electrets with different thicknesses were investigated detailedly in respect of chargeability, storage charge stability in high temperature and reliability in high humidity environment. Samples with different thicknesses of Si 3 N 4 and SiO 2 were prepared on Pyrex 7740 glass substrates and characterized by isothermal and high humidity charge decay. The results of experiment approved that the PECVD SiO 2 /Si 3 N 4 double layers electrets on glass substrate has as good chargeability and charge stability in high temperature and high humidity environment as thermal oxidation or APCVD/LPCVD ones on silicon substrates. The experiment results indicated that a Si 3 N 4 layer no less than 50 nm is necessary for good charge stability in high temperature and a Si 3 N 4 layer thicker than 500 nm decreases the chargeability. Even a 2 nm Si 3 N 4 layer is enough to significantly improve the charge stability in high humidity environment. Thick SiO 2 layer can increase the surface potential of electrets under the same charging condition and its charge stability in high temperature. However, the electrets with high surface potential also exhibit poor uniformity of charge stability in high humidity environment. PECVD, SiO 2 /Si 3 N 4 double layer, electrets, thicknesses Citation:Zou X D, Zhang J W. Study on PECVD SiO 2 /Si 3 N 4 double-layer electrets with different thicknesses.

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Section: Effect Of Different Sio 2 Thicknessesmentioning

confidence: 99%

Study on PECVD SiO2/Si3N4 double-layer electrets with different thicknesses

Zou

Zhang

2011

Sci. China Technol. Sci.

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“…The electric field in the deposited film, E2, can be related to the shift in flatband voltage, AVf,, by the simultaneous solution of equations (1), (2) and (3) The following functional fom will be assumed for the current density in the deposited film,…”

Section: Resultsmentioning

confidence: 99%

Bias Instability in Two-Layer MIS Structures

Curry¹,

Nigh²

1970

8th Reliability Physics Symposium

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MIS structures consisting of a deposited film of A1203 or Si3N4 on thermally grown Si02 were studied to determine the effect that charge accumulation at the deposited film-SiO2 interface has on the threshold voltage stability.In order to study the effects of metallization, aluminum, gold and titanium field plates were evaporated on the deposited film. The experimental data indicate that Al forms a lower potential barrier on the deposited film than any of the other metallizations tested. For a given applied bias the shift in the flatband voltage is always greater for samples contacted with aluminum. Ti contacted and Au contacted slices show similar but much smaller shifts in the flatband voltage. It was determined that the charge accumulation is a result of Schottky emission from the metaldeposited film interface. This was determined by the field dependence and supported by the bias asymmetry of the accumulated charge.As a result of this investigation it was determined that the metallization plays an important role in determing the stability of MIS devices under applied bias. However, the use of proper metallization and the selection of low operating field will reduce the accumulation to a point where it will not present a serious reliability problem.

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“…Earlier work on MNOS devices (13,14) leads investigators to conclude that the charges were trapped at the oxide nitride interface. If this were the case, then the decay of the threshold voltage would be a simple exponential characterized by a single time constant.…”

Section: Theorymentioning

confidence: 96%

The Effects of High Temperature Annealing on MNOS Devices

Topich

Yon

1976

J. Electrochem. Soc.

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The effects of high temperature annealing on the conduction and memory properties of MNOS memory devices was studied. The results showed that the conductivity of the nitride increased with annealing time and temperature and that the memory retention qualities of the device were degraded. These results can be explained by the hypothesis that the heat-treatment has increased the number of traps in the silicon nitride. The correlation of the theoretical and experimental results indicates that the traps are uniformly distributed through the silicon nitride layer and are not localized at the oxide nitride interface.Annealing as one step in the fabrication process for producing MNOS memory devices has been used by many workers in this field (1-4). However, no detailed investigation into the effects of this step on the properties of the devices was undertaken. In this study, all samples used were fabricated in an identical manner and then subjected to annealing treatments for various times from 5 to 120 rain and at various temperatures in the range 800~176After the devices were completed, the conduction and memory properties were analyzed in order to provide information about the effects of the annealing on certain parameters which characterize the silicon nitride film. Fabrication ProcedureAll devices tested were fabricated on phosphorousdoped (111) polished silicon wafers of 0.5-0.88 ohmcm resistivity. The silicon wafers were degreased using 3 min soaks in hot trichloroethelene, acetone, and methanol; followed by a rinse in deionized water down to 10 megohm-cm; a 1 min etch in buffered HF; and a second water rinse. The silicon surfaces were further cleaned using a 5 rain soak in a hot solution of 5 parts deionized water, 1 part ammonium hydroxide, and 3 parts of hydrogen peroxide; a rinse in deionized water; a 5 min soak in a hot solution of 5 parts deionized water, 1 part hydrochloric acid, and 2 parts of hydrogen peroxide; and a final rinse in deionized water.Ellipsometric measurements showed that after the cleaning procedure approximately 10A of silicon dioxide was present on the silicon surface, as has been reported by others (5, 6). Since the primary purpose of this work was to investigate the silicon nitride layer, no additional oxide was grown.Immediately after being cleaned, 750-1000A of silicon nitride was pyrolytically deposited at 700~ on the wafers using silane and ammonia with hydrogen as a carrier gas. The silane and ammonia were in the ratio of 1 to 100 and were purchased from Matherson under the trade name N-gas.Following the silicon nitride deposition, the samples were annealed in dry nitrogen at either 800 ~ , 900 ~ , 950 ~ or 1000~ for various lengths of time. For each batch of samples fabricated, one wafer was left as a control to which the experimental data could be compared. Table I lists the various samples along with their annealing temperatures and times.Next, aluminum was evaporated on top the Si3N4 and photolithography was used to outline circular electrodes 35 mils in diameter giving an are...

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Charge Storage Model for Variable Threshold Fet Memory Element

Cited by 61 publications

References 5 publications

Study on PECVD SiO2/Si3N4 double-layer electrets with different thicknesses

Study on PECVD SiO2/Si3N4 double-layer electrets with different thicknesses

Bias Instability in Two-Layer MIS Structures

The Effects of High Temperature Annealing on MNOS Devices

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