Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures

Capturing properties of a threefold coordinated silicon atom in silicon nitride: Positive correlation energy model

“…where E The N 3 Si· defect was discussed intensively in the literature as a defect responsible for the carrier localization in Si 3 N 4 films [4,8,9,18,[29][30][31]. In agreement with Pacchion and Erbetta [18], our calculations show that the N 3 Si· defect can be a trap for electrons.…”

“…Although this memory effect has been discovered for more than thirty years and is widely used in modern silicon devices [2,[4][5][6][7][8], the exact nature and the kind of defects responsible for the carrier localization in the nitride film is still controversial. However, we already had a consensus that the localization of electrons and holes in the Si 3 N 4 film is related to the intrinsic defects created by the excess silicon atoms [2,4,8,9].The intrinsic defects in amorphous solids are believed to be due to the dangling bonds. However, most of the defects could not be detected with the electron spin resonance (ESR) measurement in a number of amorphous semiconductors and wide-gap polar dielectrics such as amorphous SiO 2 and Si 3 N 4 films [1-4,10].…”

“…According to the NCE model, reaction (1) is energetically favorable in the NCE model and the charged diamagnetic defects (N 3 Si + and N 3 Si − :) are electron and hole traps which are supposed to be responsible for the memory effect in silicon nitride [2,8,[14][15][16][17]. Latest ab initio density functional theory (DFT) calculations [18] showed that the correlation energy for N 3 Si· defects is equal to 0…”

Improved Memory Characteristics by NH3Post Annealing for ZrO2Based Charge Trapping Nonvolatile Memory

“…The second category, coming from thermal excitation, is temperature dependent. Trap to band tunneling and thermal excitation are the dominant charge loss mechanisms, and jointly contribute to charge loss for memory devices [13][14][15][16]. In our case, the charge loss increased with increase of temperature resulting from thermal excitation, and more electrons were discharged via thermal excitation into the conduction band of the charge trapping layer, then tunneled back to the silicon substrate.…”

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

“…This reduces the probability of further electron injection from the trap layer, and thus more reliable charge storage can be expected [47]. The endurance characteristic of JL-SONOS is shown Figure 16(b), in which all devices can maintain the P/E window after 10 5 cycles at 85 • C. A possible 3D memory cell circuit design based on vertical SiNW JL-SONOS is illustrated in Figure 17.…”