Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Amusan, O.A.; Witulski, A.F.; Massengill, L.W.; Bhuva, B. L.; Fleming, P.R.; Alles, Michael L.; Sternberg, Andrew L.; Black, Jeffrey D.; Schrimpf, Ronald D.

doi:10.1109/tns.2006.884788

Cited by 357 publications

(132 citation statements)

References 10 publications

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“…As will be explained in Section III-C, the main cause of the MCU is charge sharing. According to [23], charge sharing strongly depends on the distance between devices, and its dependence is nonlinear. Therefore, the difference between the data patterns is less influential on the intraword MCU rate.…”

Section: B Soft-error Rate and Multiple-cell Upsetmentioning

confidence: 99%

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Fuketa

Harada

Hashimoto

et al. 2014

IEEE Trans. Device Mater. Relib.

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Abstract-This paper presents measurement results of alphaparticle-induced soft errors and multiple-cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 to 0.3 V. We reveal that the soft-error rate (SER) at 0.3 V is six times higher than that at 1.0 V and the MCU rate significantly increases in the subthreshold region. To investigate the reason for the MCU increase, the dependences of the MCU rate on the body-bias voltage and the distance between well ties are examined, and we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing. In addition, the dependence of the variation in the soft-error immunity of each memory cell on the supply voltage is examined, since SRAMs operating in the subthreshold region are sensitive to manufacturing variability. Measurement results indicate that the number of soft errors in each memory cell varies cell by cell, whereas the cause of the variation is explained by the spatial randomness of alpha-particle hits, and a distinct influence of manufacturing variability is not observed even in the subthreshold region.Index Terms-Alpha-particle-induced soft error, multiple-cell upset (MCU), soft-error rate (SER), subthreshold circuit.

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Section: B Soft-error Rate and Multiple-cell Upsetmentioning

confidence: 99%

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Fuketa

Harada

Hashimoto

et al. 2014

IEEE Trans. Device Mater. Relib.

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“…It was firstly described in [8] and it is immune to SEU caused by charge collection at a single node. However, because of the scaled technologies, charge sharing is becoming more and more prominent [9]. The adjacent transistors among the sensitive transistors also collect charge simultaneously, which may significantly affect the SEU sensitivity of the DICE flip-flop.…”

Section: Introductionmentioning

confidence: 99%

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

Cai

Chen

2017

IEICE Electron. Express

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This paper studies the impact of adjacent transistors on the SEU sensitivity of the DICE flip-flop. We compare the SEU sensitivity of the DICE flip-flop with two different layout topologies. Heavy ion experiment results indicate the separation layout topology can reduce the SEU sensitivity of the DICE flip-flop, both in SEU threshold and SEU cross section. TCAD simulation is used to investigate the mechanisms. Simulation results indicate the higher charge collection capability of adjacent transistors in the separation layout topology is the main reason to reduce the SEU sensitivity.

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“…Due to the scaled device size, the charge sharing effect has become a great concern [1,2,3]. It can weaken the hardening performance of many radiation hardened techniques.…”

Section: Introductionmentioning

confidence: 99%

DICE-based test structure to measure the strength of charge sharing effect

Yun

Liang

2015

IEICE Electron. Express

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With the technology scaling, the charge sharing effect is becoming more prominent. Using the property of DICE latch, we present a DICEbased test structure to measure the strength of charge sharing effect. Threedimensional TCAD simulations are done to simulate the DICE property. And a test chip is fabricated by the commercial 65 nm bulk CMOS process to verify our proposed test structure. Heavy-ion experiment results indicate that this test structure is efficient to obtain the strength of charge sharing effect.

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Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Cited by 357 publications

References 10 publications

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

DICE-based test structure to measure the strength of charge sharing effect

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